Netlist Optimization by Gate Merging

Conceicao, Calebe; Reis, Ricardo

doi:10.1109/vlsi-soc.2019.8920291

Cited by 2 publications

(2 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Eight different error metrics, including mean absolute error (MAE), error probability (EP), standard deviation (STD), mean relative error (MRE), median of absolute error (MeAE), mode of absolute error (MoAE), maximum absolute error (Max-AE), and minimum absolute error (Min-AE) were investigated for eVar, and BwF-modified CGP and traditional CGP configurations for the power and activation functions. The error metrics are defined in Equation (6).…”

Section: Resultsmentioning

confidence: 99%

“…The standard rule-based and top-down synthesis flow [1][2][3][4][5][6] is adopted regularly for realizing various arithmetic and logical functions, including higher operand bit-widths. However, these methods neither allow any room to augment custom cells toward arriving at the hierarchical design nor offer any design-space exploration to realize the hardwarereliable design.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP

Prashanth,

Rao

2024

IET Computers & Digital Techniques

View full text Add to dashboard Cite

Unconventional functions, including activation functions and power functions, are extremely hard-to-realize primarily due to the difficulty in arriving at the hierarchical design. The hierarchical design allows the synthesis tool to map the functionality with that of standard cells employed through the regular ASIC synthesis flow. For conventional functions, the hierarchical design is structured and then supplied to the synthesis flow, whereas, for unconventional functions, the same method is not reliable, since the current synthesis method does not offer any design-space exploration scheme to arrive at an easy-to-realize design entity. The unconventional functions either take a long synthesis run-time or additional efforts are spent in restructuring the hierarchical design for the desired function to synthesizable ones. Cartesian genetic programing (CGP) allows to not only incorporate custom logic gates for synthesizing the hierarchical design but also aids in the design-space exploration for the targeted function through the custom gates. The CGP configuration evolves difficult-to-realize complex functions with multiple solutions, and filtering through desired Pareto-optimal requirements offers a unique hierarchical design. Incorporating CGP-derived hierarchical designs into the traditional synthesis flow is instrumental for implementing and evaluating higher-order designs comprising nonlinear functional constructs. Six activation functions and power functions that fall in the category of unconventional functions are realized by the CGP method using custom cells to demonstrate the capability. Further, the hierarchical design of these unconventional functions is flattened and compared with the same function that is directly synthesized using basic gates. The CGP-derived synthesis method reports 3× less synthesis time for realizing the complex functions at the hierarchical level compared to the synthesis using basic gate cells. Hardware characteristics and error metrics are also investigated for the CGP realized complex functions and are made freely available for further usage to the research and designers’ community.

show abstract

Section: Resultsmentioning

confidence: 99%