Network accelerator for parallel discrete event simulations

Abstract

The simulation time of parallel and distributed discrete event simulation is the heart rate for as-fast-as execution schemes. Agreeing upon a global simulation time and distributing it to the simulation processes can be improved by exploiting or redesigning the network hardware. In this paper, we present such an approach that o oads simulation time calculations to network switches in order to speed up the steps where time advance requests are made and time advance grants are waited. By reducing the waiting time for time advancement, we aim to improve the overall performance of the parallel simulations. The measurements from the FPGA-based hardware setup and the results from our network simulations show that overall performance can be improved when time management calculations are o oaded to the network switches. Additionally, the transient message problem is also solved within the network by not allowing the time control messages to bypass the time-dependent events. The network acceleration of the region-based event distribution is also studied, and o oading the region matching tasks to the network switches is found to be feasible to reduce the costs of node-based calculations, especially for fast-moving regions. In this study, we consider High-Level Architecture (HLA) for simulation infrastructure and fat tree topology for high-performance networking.Data Distribution Management (DDM) services are de ned under federate interface speci cations. TM service is responsible for message ordering in the time domain. DDM service is responsible for implementing effective data exchange algorithms between federates. This includes matching, message ltering, and multicast group planning. TM and DDM services are the dominating factors for network tra c and overall performance of a simulation.Initially designed for integrating different simulators together, the HLA found an alternative usage for parallelizing a single simulation. For instance, a new production line planning simulation to verify the required product quantities could be sped up by the HLA [3]. On the integration side, co-simulating analog, digital, and RF components of a System On Chip (SoC) IC is possible since the HLA framework has well de ned interfaces [4], and allows for the simple integration and testing of a variety of simulators and models. Additionally, hybrid co-simulation of Matlab Simulink continuous time domain designs and discrete event designs is also possible [5]. The simulations which are impossible to run in only one simulation environment can be easily integrated with HLA. Smart grid application for the cyber-physical energy system simulation is based on HLA to cosimulate the different simulation environments [6].Continuous time-domain application of power system and discrete event application of internet and communication technologies (ICT) co-simulation runs on a real-time environment together on HLA. An alternative would be to cosimulate the power system and ICT using the system on the loop (SITL).Although SITL provides real-time hardware-i...