Network on Chip and Parallel Computing in Embedded Systems

Belkacemi, Dihia; Bouchebaba, Youcef; Daoui, Mehammed; Lalam, Mustapha

doi:10.1109/mcsoc.2016.53

Cited by 7 publications

(3 citation statements)

References 18 publications

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“…The different working principles of the metaheuristic algorithms condition their final output. According to works [2], [5], to find the most complete sets of solutions, different algorithms should be used for the same problem. Thus, all the aforementioned algorithms are used, but only a few of them are shown in the results in Section V-D due to visualization purposes.…”

Section: Background a Ddr3 Sdram Device Addressingmentioning

confidence: 99%

“…As well, a differentiation of the DDR memory request types (e.g., read, write, row switch) is done (see Section IV-A and Table I). Due to space constraints, the development and evaluation of the self-developed cost function is omitted 2 . Thus, we jump directly to Equation 2, which computes the interference cost for a given task through the addition of the intra-bank (IC intra (τ i )) and inter-bank (IC inter (τ i )) interference.…”

Section: B Cost Functionsmentioning

confidence: 99%

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Task and Memory Mapping Optimization for SDRAM Interference Minimization on Heterogeneous MPSoCs

Gonzalez

Chaudron

Boniol

et al. 2022

2022 IEEE 27th International Conference on Emerging Technologies and Factory Automation (ETFA)

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DDR SDRAM memories are resources commonly used on multicore platforms and hence, being a main source of interference. To deal with this issue, we propose a methodology based on task/memory mapping optimization through multiobjective heuristic-based algorithms. By placing the tasks on the platform cores and the memory in the DDR SDRAM banks, we minimize the DDR SDRAM interference while considering other aspects such as the task execution parallelism and deadline margin. To evaluate the fitness of the task/memory map, the optimization algorithms make use of cost function equations. In order to compute the DDR memory interference cost, we use a fast executing self-designed cost function. The execution parallelism is computed using the workload variance cost function. The deadline margin of a task is computed considering the inter and intra core interference. The task/memory mapping outcomes are checked through tests for which the heterogeneous MPSoCs Keystone II and Sitara AM5728 are used. To assure certification, the WCET constraints of the resulting near-optimal Pareto solutions are verified through formally validated bounding frameworks.

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Section: Background a Ddr3 Sdram Device Addressingmentioning

confidence: 99%

Section: B Cost Functionsmentioning

confidence: 99%

Task and Memory Mapping Optimization for SDRAM Interference Minimization on Heterogeneous MPSoCs

Gonzalez

Chaudron

Boniol

et al. 2022

2022 IEEE 27th International Conference on Emerging Technologies and Factory Automation (ETFA)

View full text Add to dashboard Cite

show abstract

“…Parallel processor system has been the widely accepted approach to increase computational capability, implemented in almost every personal computer. Embedded processor as one of the crucial components in IoT adopts the same approach in the form of multi-processor system-on-chip (MPSoC) [9], a single integrated circuit containing multiple processors and other elements such as input-output (IO) and memory [10]. MPSoCs has been widely developed and used in various applications such as LTE modem [11], ECG analysis [12], image processing [13,14].…”

Section: Introductionmentioning

confidence: 99%

Multicore development environment for embedded processor in arduino IDE

et al. 2020

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Internet of things (IoT) technology has found more applications that require complex computation while still preserving power. Embedded processors as the core of the IoT system approaches the need for computation by employing a parallel processor system, namely MPSoC. While various MPSoCs hardware is widely available, there is limited software support form of user-friendly libraries and development platform. There is a need for such a platform to facilitate both the study and development of parallel embedded software. arduino as the widely used embedded development platform is yet to officially support multicore programming. This work proposes an arduino-based development environment that supports multicore programming while maintaining arduino's simple program structure, targeted at specific low-power MPSoC, the RUMPS401. The environment is fully functional, and while it targets only specific MPSoC, the proposed environment can easily be adopted to other MPSoCs with similar structures with minimal modification.

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Parallel Applications Mapping onto Heterogeneous MPSoCs Interconnected Using Network on Chip

Belkacemi

Daoui

Bouzefrane

2021

Lecture Notes in Computer Science

Self Cite

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To meet the growing requirements of today's applications, multiprocessor architectures (MPSoCs) interconnected with a network on chip (NoC) are considered as a major solution for future powerful embedded systems. Mapping phase is one of the most critical challenge in designing these systems. It consists of assigning application' tasks on the target platform which can have a considerable influence on the performance of the final system. Due to the large solutions' research space generated by both the application complexity and the platforms, this mapping phase can no longer be done manually and hence it requires powerful exploration tools called DSE (Design Space Exploration Environment). This paper proposes a new tool for static mapping applications on NoC based on heterogeneous MPSoCs. This tool integrates several multiobjective optimization algorithms that can be specified in order to explore different solutions' spaces, mainly: exact method, metaheuristics (population-based metaheuristics and single solution-based ones) as well as hybrid ones; it offers different cost functions (defined using analytical or simulation models). The user can specify them or define others easily and it provides an easy way to evaluate the performance of the Pareto front returned by different algorithms using multiple quality indicators. We also present a series of experiments by considering several scenarios and give guidelines to designers on choosing the appropriate algorithm based on the characteristics of the mapping problem considered.

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Network on Chip and Parallel Computing in Embedded Systems

Cited by 7 publications

References 18 publications

Task and Memory Mapping Optimization for SDRAM Interference Minimization on Heterogeneous MPSoCs

Task and Memory Mapping Optimization for SDRAM Interference Minimization on Heterogeneous MPSoCs

Multicore development environment for embedded processor in arduino IDE

Parallel Applications Mapping onto Heterogeneous MPSoCs Interconnected Using Network on Chip

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