Network-on-Chip: Power Optimization Architecture Mapping based on Global Interconnection Links

Saad, EI Sayed M.; Awadalla, Medhat; Salem, SamehA.; Mostafa, Ahmed M.

doi:10.7763/ijcee.2011.v3.329

Cited by 1 publication

(3 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A new optimization algorithm to find the network topology and the PEs mapping that matches the traffic characteristics of the NoC-based system and gives the lowest power consumption on the global interconnection links, is developed in [5]. The optimization algorithm explores NoC application synthesis and mapping to nine standard topologies.…”

Section: Application-specific Task Mapping Techniquementioning

confidence: 99%

“…Step 5: Generate the initial mapping A heuristic algorithm to find the initial mapping which is close to the optimum mapping is developed [5]. In this algorithm, the PE with the maximum traffic is placed onto the location with best connectivity (has minimum total connectivity from the connectivity matrix) and has number of neighbors that best match the number of PEs directly connected to it.…”

Section: B Optimization Algorithmmentioning

confidence: 99%

“…This paper integrate the mapping technique developed in [5] with the POPM routing algorithm in order to analyze the impact of their joint application on the network performance and power consumption. The proposed technique is verified through four different video processing applications [23]: MPEG4, VOPD, MWD, and PIP.…”

mentioning

confidence: 99%

See 2 more Smart Citations

C26. An Integrated Power-efficient Mapping and Routing Technique for Mesh-based Networks-on-Chip

Saad

Salem

Awadalla

et al. 2013

2013 30th National Radio Science Conference (NRSC)

Self Cite

View full text Add to dashboard Cite

As technology moves towards multi-core system-on-chips (SoCs), networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. One of the most trade-off aspects in the design of NoCs is the improvement of the network performance, in terms of throughput and latency, while minimizing power consumption. This paper proposes an integrated power-efficient mapping and routing technique for mesh-based Networks-on-Chip. This technique combines an oblivious, path-diverse, minimal routing algorithm with a mapping approach that achieves the lowest power consumption in terms of the communication traffic on the global interconnection links. The robustness and reliability of the proposed technique is verified in the context of four different video processing applications: MPEG4, VOPD, MWD, and PIP. The experimental results show that the proposed integrated technique significantly improves network performance and power consumption.

show abstract

Section: Application-specific Task Mapping Techniquementioning

confidence: 99%

Section: B Optimization Algorithmmentioning

confidence: 99%