Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip

Abstract

This paper proposes a multiobjective application mapping technique targeted for large-scale network-on-chip (NoC). As the number of intellectual property (IP) cores in multiprocessor system-on-chip (MPSoC) increases, NoC application mapping to find optimum core-to-topology mapping becomes more challenging. Besides, the conflicting cost and performance trade-off makes multiobjective application mapping techniques even more complex. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA). The initial population of GA is initialized with network partitioning (NP) while the crossover operator is guided with knowledge on communication demands. NP reduces the large-scale application mapping complexity and provides GA with a potential mapping search space. The proposed genetic operator is compared with stateof-the-art genetic operators in terms of solution quality. In this work, multiobjective optimization of energy and thermal-balance is considered. Through simulation, knowledge-based initial mapping shows significant improvement in Pareto front compared to random initial mapping that is widely used. The proposed knowledge-based crossover also shows better Pareto front compared to state-of-the-art knowledge-based crossover.

Clustered Networks-on-Chip: Simulation and Performance Evaluation

“…We further want to extend the simulator to support dynamic clustering, dynamic scaling, resource borrowing, and the ability to configure different NoC clusters with different configurations. As for clustering technique, we aim at supporting the techniques mentioned in [13]- [17], [19], [27]- [30], and allowing users to specify their own custom technique as well.…”

Application Profiling and Mapping on NoC-based MPSoC Emulation Platform on Reconfigurable Logic

“…Task mapping technique can be classified into design time mapping, run-time mapping and hybrid mapping. In design time mapping [5][6][7][8][9], the mapping process is performed off-line to facilitate better decision in using system resources. Design time mapping is suitable for static workload scenarios having a predefined task graph and static platform (i.e., both applications and platform do not change in time).…”

“…Most mapping methodologies in literatures e.g. [5][6][7][8][9][10][11][12][13] assumed a specific program execution while the communication cost was considered constant across platform. As practical behaviour of applications may differ compared to its specified task graph, there are different methods in literatures extracting application run-time metrics prior to the mapping exploration.…”