Networks on Chips for High-End Consumer-Electronics TV System Architectures

Abstract

Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SOCs are application-specific standard products (ASSPs) with limited programmability. We describe why TV SOCs must become more flexible, and why companion chips together with networks on chips (NOC) are a crucial enabling technology. In particular; networks that span multiple chips will become important in the nearfuture.We demonstrate our ideas by extending a commerciallyavailable SOC for picture improvement in high-end TVs with the ,Ethereal NOC. Ourfirst unoptimised results indicate that replacing the original interconnect (consisting of dedicated links and multiplexers for bypasses) by programmable NOC increases the SOC area by 4% and its power dissipation by 12%. The new, flexible SOC allows new tasks to be spliced in at any point in the task graph. Both analytical performance verification and system simulations at RTL VHDL show that the extended SOC meets its functional requirements. Using the AEthereal design flow the extended architecture was designed, implemented, and verified in 12 person months.To the best of our knowledge, this is the first application of a NOC to a commercial SOC. The quantitive results indicate that even retrofitting a NOC to an existing architecture is beneficial at acceptable cost.

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

“…The NI, clock domain crossing, shell, and IPs with streaming ports (like the µblaze in our example system or the video blocks in [40]) all make direct use of this stack. The data-link layer governs the flow control of individual words of streaming data.…”

“…Third, SoCs are evolving in the direction of distributed-memory architectures, offering high throughput and low latency [22,39], coupled with a low power consumption [23]. Fourth, address-less streaming communication between IPs is growing in importance to alleviate contention for shared memories and is becoming a key aspect in achieving efficient parallel processing [18,40].…”

Layout aware design of mesh based NoC architectures

“…Angiolini et al [11] compared the power and performance of mesh based NoC architectures with AMBA bus architectures. Steenhof et al [12] proposed NoC as a solution to high-end consumer electronics systems, and presented a SoC with mesh based NoC for a TV system architecture. Lee et al [13] implemented a SoC with a hierarchical star based NoC topology.…”

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

“…By using the interconnection network as the communication infrastructure between cores, Networks-on-Chip (NoCs) are emerging as an efficient and scalable alternative to existing on-chip interconnects which allow systems to be designed modularly. Different NoCs solutions are used in MPSoC platforms and commercialized by many companies such as SonicsGN [5] developed by Sonics, FlexNoC [6] by Arteris, AEthereal NoC [7] by Philips Research Laboratories and Teraflops Research Chip (also called Polaris) [8,9] by Intel Corporation's TeraScale Computing Research Program. Other NoC-based multicore system architectures are developed by teams from universities and research institutions such as SoCIN [10], OCCN [11], FAUST [12] and Ninesilica [13].…”