NeuFlow: Dataflow vision processing system-on-a-chip

Pham, Phi-Hung; Jelaca, Darko; Farabet, Clément; Martini, Berin; LeCun, Yann; Culurciello, Eugenio

doi:10.1109/mwscas.2012.6292202

Cited by 74 publications

(55 citation statements)

References 4 publications

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“…This architecture's data I/O bandwidth of 525 MB/s full-duplex for 203 GOp/s, 2.58 MB/GOp, is far better than the results shown in previous work, such as 24.7 MB/GOp for the neuFlow ASIC [16] or 20 MB/GOp for nn-X [17].…”

Section: Resultscontrasting

confidence: 54%

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Origami

Cavigelli

Gschwend

Mayer

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

130

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Today advanced computer vision (CV) systems of ever increasing complexity are being deployed in a growing number of application scenarios with strong real-time and power constraints. Current trends in CV clearly show a rise of neural network-based algorithms, which have recently broken many object detection and localization records. These approaches are very flexible and can be used to tackle many different challenges by only changing their parameters. In this paper, we present the first convolutional network accelerator which is scalable to network sizes that are currently only handled by workstation GPUs, but remains within the power envelope of embedded systems. The architecture has been implemented on 3.09 mm 2 core area in UMC 65 nm technology, capable of a throughput of 274 GOp/s at 369 GOp/s/W with an external memory bandwidth of just 525 MB/s full-duplex -a decrease of more than 90% from previous work.

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Section: Resultscontrasting

confidence: 54%

“…A popular architecture is the one which started as CNP [14] and was further improved and renamed to NeuFlow [15], [16] and later on nn-X [17].…”

Section: Fpga Implementationsmentioning

confidence: 99%

Origami

Cavigelli

Gschwend

Mayer

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

130

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“…Many approaches have been proposed to accelerate the computation or reduce the memory footprint and storage size of DNNs. One approach from the hardware perspective is designing hardware accelerators for the computationally expensive operations in DNNs [19,20,21]. From the algorithmic perspective, a popular route to faster and smaller models is to impose constraints on the parameters of a DNN to reduce the number of free parameters and computational complexity, like low-rankness [22,23,24,25,26,27], sparsity [28,29,30,31], circulant property [32], and sharing of weights [33,34].…”

Section: Introductionmentioning

confidence: 99%

Balanced Quantization: An Effective and Efficient Approach to Quantized Neural Networks

Zhou

Wang

et al. 2017

J. Comput. Sci. Technol.

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Quantized Neural Networks (QNNs), which use low bitwidth numbers for representing parameters and performing computations, have been proposed to reduce the computation complexity, storage size and memory usage. In QNNs, parameters and activations are uniformly quantized, such that the multiplications and additions can be accelerated by bitwise operations. However, distributions of parameters in Neural Networks are often imbalanced, such that the uniform quantization determined from extremal values may under utilize available bitwidth. In this paper, we propose a novel quantization method that can ensure the balance of distributions of quantized values. Our method first recursively partitions the parameters by percentiles into balanced bins, and then applies uniform quantization. We also introduce computationally cheaper approximations of percentiles to reduce the computation overhead introduced. Overall, our method improves the prediction accuracies of QNNs without introducing extra computation during inference, has negligible impact on training speed, and is applicable to both Convolutional Neural Networks and Recurrent Neural Networks. Experiments on standard datasets including ImageNet and Penn Treebank confirm the effectiveness of our method. On Ima-1 arXiv:1706.07145v1 [cs.CV] 22 Jun 2017 geNet, the top-5 error rate of our 4-bit quantized GoogLeNet model is 12.7%, which is superior to the state-of-the-arts of QNNs.

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“…It can be clearly seen that the typical on-chip (L1, L2) storages in the memory hierarchy (caches or SRAM-based scratchpad memories) cannot accommodate even a single layer of these ConvNets, as the required storages per layer range from 6 MB to over 300 MB. In addition, the assumption that all coefficients can be stored on-chip ( [16][17] [34]) is not valid anymore, since an additional storage of 14 ∼ 280 MB is required to accommodate the coefficients. Overall, 16∼580 MB is needed for layer-by-layer execution, demonstrating that DRAM is necessary as the main storage for deep ConvNets and also motivating computation near main memory.…”

Section: B Implementation Challenges Of Modern Convnetsmentioning

confidence: 99%

Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes

Azarkhish

Rossi

Loi

et al. 2018

IEEE Trans. Parallel Distrib. Syst.

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Abstract-High-performance computing systems are moving towards 2.5D and 3D memory hierarchies, based on High Bandwidth Memory (HBM) and Hybrid Memory Cube (HMC) to mitigate the main memory bottlenecks. This trend is also creating new opportunities to revisit near-memory computation. In this paper, we propose a flexible processor-in-memory (PIM) solution for scalable and energy-efficient execution of deep convolutional networks (ConvNets), one of the fastest-growing workloads for servers and high-end embedded systems. Our codesign approach consists of a network of Smart Memory Cubes (modular extensions to the standard HMC) each augmented with a many-core PIM platform called NeuroCluster. NeuroClusters have a modular design based on NeuroStream coprocessors (for Convolution-intensive computations) and general-purpose RISC-V cores. In addition, a DRAM-friendly tiling mechanism and a scalable computation paradigm are presented to efficiently harness this computational capability with a very low programming effort. NeuroCluster occupies only 8% of the total logic-base (LoB) die area in a standard HMC and achieves an average performance of 240 GFLOPS for complete execution of full-featured state-of-the-art (SoA) ConvNets within a power budget of 2.5 W. Overall 11 W is consumed in a single SMC device, with 22.5 GFLOPS/W energy-efficiency which is 3.5X better than the best GPU implementations in similar technologies. The minor increase in system-level power and the negligible area increase make our PIM system a cost-effective and energy efficient solution, easily scalable to 955 GFLOPS with a small network of just four SMCs.

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NeuFlow: Dataflow vision processing system-on-a-chip

Cited by 74 publications

References 4 publications

Origami

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Balanced Quantization: An Effective and Efficient Approach to Quantized Neural Networks

Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes

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