Neural Dynamics in Reconfigurable Silicon

Abstract

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

Finding a roadmap to achieve large neuromorphic hardware systems

“…The STLS are modified EEPROM devices, fabricated in a standard CMOS process, that simultaneously provide long-term storage (non-volatile), computation, and adaptation in a single device. The development of Large-Scale Field Programmable Analog Arrays (FPAA) enabled configuration to be used for physically based neuromorphic techniques (Twigg et al, 2007; Basu et al, 2010a,b; Schlottmann et al, 2010, 2012a,b, c; Wunderlich et al, 2012). These approaches allow the added advantage of those building applications not to have expertise in IC design, a separation that should prove useful for the neuromorphic community as well.…”

A mixed-signal implementation of a polychronous spiking neural network with delay adaptation

“…Other factors, such as the accuracy and the bandwidth of the converters, will lead to the requirement for a high precision ADC. The second possible solution is to use floating-gate devices, which employ programmable elements that that could be used to store the analog values in a non-volatile memory (Basu et al, 2010; Brink et al, 2013; Hasler and Marr, 2013). This feature is a promising alternative for the implementation of our polychronous spiking neural network.…”

“…Some programmable platforms using floating gates (Basu et al, 2010; Brink et al, 2013). Furthermore, most of these systems use DACs to configure the analog modules to emulate different biological behaviors.…”

Low Cost Interconnected Architecture for the Hardware Spiking Neural Networks

“…Recently, researchers have attempted to use custom hardware to design the SNNs, e.g., ASIC and FPGA devices. For the former, many approaches have been proposed, e.g., TrueNorth chips ( Merolla et al, 2014 ; Akopyan et al, 2015 ), a neuromorphic analog chip ( Basu et al, 2010 ) and Neurogrid, a large-scale neural simulator based on a mixed analog-digital multichip system ( Benjamin et al, 2014 ). The main disadvantage of using ASIC devices is the high cost for the development and chip manufacturing as a tiny change would lead to a new development cycle ( Pande et al, 2013 ).…”