Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning

Abstract

We designed a simple neural segmentation model that is suitable for analog circuit implementation. The model consists of excitable neural oscillators and adaptive synapses, where the learning is governed by a symmetric spike-timing dependent plasticity (STDP). We numerically demonstrate basic operations of the proposed model as well as fundamental circuit operations using a simulation program with integrated circuit emphasis (SPICE).

A time-domain analog weighted-sum calculation circuit using ferroelectric-gate field-effect transistors for artificial intelligence processors

“…On the other hand, general purpose neuromorphic AI processors, such as Intel's Loihi, 23) and other neuromorphic processors have on-chip learning functions such as spike-timing dependent synaptic plasticity. 14,[24][25][26][27] Although all the current AI processors were developed using digital approaches, if analog AI processors are developed, the conditions required for analog memory devices on a chip will be different in these two processor types. For off-chip learning chips, arbitrary weight values are set and held in analog memory devices, because the function installed in such a chip is inference using synaptic weights trained in the server.…”