Neuromorphic Technology Based on Charge Storage Memory Devices

Lee, Sung-Tae; Lim, Suhwan; Choi, Nagyong; Bae, Jong-Ho; Kim, Chul-Heung; Soo-Chang, Lee; Lee, Dong Hwan; Lee, Tackhwi; Chung, Sungkwon; Park, Byung‐Gook; Lee, Jong-Ho

doi:10.1109/vlsit.2018.8510667

Cited by 20 publications

(12 citation statements)

References 3 publications

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“…In prior studies, our group has reported neuromorphic architectures that use NAND flash memory cells as binary synapses performing XNOR operation in BNNs (Lee et al, 2019a) and synaptic devices in on-chip training (Lee et al, 2018). In those studies, output current for each neuron is sequentially generated each time V read is imposed on a selected WL.…”

Section: Comparison With Prior Workmentioning

confidence: 99%

“…However, in this work, all outputs of neurons in a neuron layer are generated in a single input pulse. In addition, in the previous study of Lee et al (2018), the conductance of synaptic devices is changed by applying an identical pulse to the synaptic device in on-chip learning. In this study, the conductance of synapse is tuned by the RVW method in off-chip learning.…”

Section: Comparison With Prior Workmentioning

confidence: 99%

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Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

Lee

2020

Front. Neurosci.

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A novel operation scheme is proposed for high-density and highly robust neuromorphic computing based on NAND flash memory architecture. Analog input is represented with time-encoded input pulse by pulse width modulation (PWM) circuit, and 4-bit synaptic weight is represented with adjustable conductance of NAND cells. Pulse width modulation scheme for analog input value and proposed operation scheme is suitably applicable to the conventional NAND flash architecture to implement a neuromorphic system without additional change of memory architecture. Saturated current-voltage characteristic of NAND cells eliminates the effect of serial resistance of adjacent cells where a pass bias is applied in a synaptic string and IR drop of metal wire resistance. Multiply-accumulate (MAC) operation of 4-bit weight and width-modulated input can be performed in a single input step without additional logic operation. Furthermore, the effect of quantization training (QT) on the classification accuracy is investigated compared with post-training quantization (PTQ) with 4-bit weight. Lastly, a sufficiently low current variance of NAND cells obtained by the read-verify-write (RVW) scheme achieves satisfying accuracies of 98.14 and 89.6% for the MNIST and CIFAR10 images, respectively.

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Section: Comparison With Prior Workmentioning

confidence: 99%

Section: Comparison With Prior Workmentioning

confidence: 99%

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

Lee

2020

Front. Neurosci.

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“…On the other hand, NAND flash memory reduces ground wires and bitlines, exhibiting a great advantage in cell density. In our previous works, we reported synaptic architectures which utilize NAND flash memory cells as synaptic devices in on-chip learning [36] and binary synapses for XNOR operation with a sequential reading scheme [37]. In these works, the VMM operation is performed sequentially.…”

Section: A Comparison With Previous Workmentioning

confidence: 99%

“…In the parallel scheme, when Vread is applied to the word-line, outputs for all neurons in the post synaptic neuron layer are produced at once. Furthermore, in the on-chip leaning of [36], the conductance of the synaptic devices is updated using only one program pulse during the training process. In this work, the RVW method is used to transfer the weights obtained from off-chip learning to the synaptic devices.…”

Section: A Comparison With Previous Workmentioning

confidence: 99%

NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)

et al. 2020

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We propose a novel synaptic architecture based on a NAND flash memory for highly robust and high-density quantized neural networks (QNN) with 4-bit weight and binary neuron activation, for the first time. The proposed synaptic architecture is fully compatible with the conventional NAND flash memory architecture by adopting a differential sensing scheme and a binary neuron activation of (1, 0). A binary neuron enables using a 1-bit sense amplifier, which significantly reduces the burden of peripheral circuits and power consumption and enables bitwise communication between the layers of neural networks. Operating NAND cells in the saturation region eliminates the effect of metal wire resistance and serial resistance of the NAND cells. With a read-verify-write (RVW) scheme, low-variance conductance distribution is demonstrated for 8 levels. Vector-matrix multiplication (VMM) of a 4-bit weight and binary activation can be accomplished by only one input pulse, eliminating the need of a multiplier and an additional logic operation. In addition, quantization training can minimize the degradation of the inference accuracy compared to post-training quantization. Finally, the low-variance conductance distribution of the NAND cells achieves a higher inference accuracy compared to that of resistive random access memory (RRAM) devices by 2~7 % and 0.04~0.23 % for CIFAR 10 and MNIST datasets, respectively. INDEX TERMS NAND flash, neuromorphic, synaptic device, hardware neural network, in-memory computing, quantized neural networks, deep neural network

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“…NAND flash memory offers ultra-high bit density for ample data storage and low fabrication cost per bit, and it has been well known as a mature technology [15]- [17]. In previous research, we reported neuromorphic systems utilizing NAND flash memory as a multi-level synapse for on-chip learning [18] and as a binary synaptic device for BNN digitally [19]. First, in this study, we propose an analog bit-counting scheme with a synaptic architecture utilizing NAND flash memory.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Binary Neuron Circuit With Adjustable Threshold for Binary Neural Networks Using NAND Flash Memory

2020

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Recent studies have demonstrated that binary neural networks (BNN) could achieve a satisfying inference accuracy on representative image datasets. BNN conducts XNOR and bit-counting operations instead of high-precision vector-matrix multiplication (VMM), significantly reducing the memory storage. In this work, an analog bit-counting scheme is proposed to decrease the burden of neuron circuits with a synaptic architecture utilizing NAND flash memory. A novel binary neuron circuit with a double-gate positive feedback (PF) device is demonstrated to replace the sense amplifier, adder, and comparator, thereby reducing the burden of the complementary metal-oxide semiconductor (CMOS) circuits and power consumption. By using the double-gate PF device, the threshold voltage of the neuron circuits can be adaptively matched to the threshold value in the algorithms eliminating the accuracy degradation introduced by the process variation. Thanks to the super-steep SS characteristics of the PF device, the proposed neuron circuit with the PF device has an off-state current of 1 pA, representing 10 5 times improvement compared to the neuron circuit with a conventional metal-oxide-semiconductor field effect transistor (MOSFET) device. A system simulation of a hardware-based BNN shows that the lowvariance conductance distribution (8.4 %) of the synaptic device and the adjustable threshold of the neuron circuit implement a highly efficient BNN with a high inference accuracy.

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Neuromorphic Technology Based on Charge Storage Memory Devices

Cited by 20 publications

References 3 publications

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)

Low-Power Binary Neuron Circuit With Adjustable Threshold for Binary Neural Networks Using NAND Flash Memory

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