NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators

Xiao, Shanlin; Guo, Yuhao; Liao, Wenkang; Deng, Huipeng; Luo, Yi; Zheng, Huanliang; Wang, Jian; Cheng, Li; Li, Gezi; Yu, Zhiyi

doi:10.1109/tvlsi.2020.3008185

Cited by 19 publications

(5 citation statements)

References 30 publications

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“…The NoC is capable of configuring the network topology based on the needs. The NeuronLink [25] is a chipto-chip interconnection network for large neural networks that support both interchip and intrachip communication. Each chip consists of 16 PEs in a mesh topology, and 4 such chips are connected in a star topology to handle a large amount of unicast and multicast traffic.…”

Section: Related Workmentioning

confidence: 99%

“…Various routing methods are adopted to fulfill the communication needs, especially multicast and gather traffic, in a DNN accelerator. Research in [25] adopts XY routing for unicast traffic and a table-based routing for multicast traffic. However, another study [17] proposes different NoC configurations for each datatype i.e, input activation, weights, and partial sums.…”

Section: Related Workmentioning

confidence: 99%

“…Since the field of DNNs is evolving rapidly, hardware design should also be able to maintain this pace. As widely adopted NoC topology, mesh is used in most of the recently proposed DNN accelerators [13] [14] [25] [23] [31]. As manyto-one and one-to-many traffic are not inherently supported in a mesh topology, one-to-many has many solutions [15] that can be well adapted to DNN workloads, but manyto-one does not have an efficient method.…”

Section: Related Workmentioning

confidence: 99%

“…We compare the proposed method and repetitive unicast method in terms of the runtime latency and power consumption. We assume that there is a higher level entity or a mapping framework similar to [16] [18] [25] [26] [32] exists that does the task of mapping neurons to the PEs, controlling timing for better synchronization without stalls, so that our focus is on evaluating the performance of the onchip network. In order to fully utilize the spatial PE arrays, the parameters obtained from Pytorch framework [37] are used to model the traces for the NoC.…”

Section: Experiments Setupmentioning

confidence: 99%

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Data Streaming and Traffic Gathering in Mesh-based NoC for Deep Neural Network Acceleration

Tiwari,

Yang,

Wang

et al. 2021

Preprint

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The increasing popularity of deep neural network (DNN) applications demands high computing power and efficient hardware accelerator architecture. DNN accelerators use a large number of processing elements (PEs) and on-chip memory for storing weights and other parameters. As the communication backbone of a DNN accelerator, networks-on-chip (NoC) play an important role in supporting various dataflow patterns and enabling processing with communication parallelism in a DNN accelerator. However, the widely used mesh-based NoC architectures inherently cannot support the efficient one-to-many and many-to-one traffic largely existing in DNN workloads. In this paper, we propose a modified mesh architecture with a one-way/two-way streaming bus to speedup one-tomany (multicast) traffic, and the use of gather packets to support many-to-one (gather) traffic. The analysis of the runtime latency of a convolutional layer shows that the two-way streaming architecture achieves better improvement than the one-way streaming architecture for an Output Stationary (OS) dataflow architecture. The simulation results demonstrate that the gather packets can help to reduce the runtime latency up to 1.8 times and network power consumption up to 1.7 times, compared with the repetitive unicast method on modified mesh architectures supporting two-way streaming.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Experiments Setupmentioning

confidence: 99%

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Data Streaming and Traffic Gathering in Mesh-based NoC for Deep Neural Network Acceleration

Tiwari,

Yang,

Wang

et al. 2021

Preprint

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“…The interfacing of OPC collaborates with NoC, this is associated with the core. The global science (GS) network and the built environment (BE) network are the two main components of any NoC network [7], [8]. The virtual channels support the connection-oriented GS services, these services are measured with the latency and hard information that promises better utilization.…”

Section: Introductionmentioning

confidence: 99%

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

Patil,

Sandi

2024

IJRES

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The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.

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Performance Evaluation in 2D NoCs Using ANN

Kale

Hazarika

Jain

et al. 2022

Lecture Notes in Networks and Systems

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NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators

Cited by 19 publications

References 30 publications

Data Streaming and Traffic Gathering in Mesh-based NoC for Deep Neural Network Acceleration

Data Streaming and Traffic Gathering in Mesh-based NoC for Deep Neural Network Acceleration

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

Performance Evaluation in 2D NoCs Using ANN

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