Neutral‐Point‐ClampedDC–ACPower Converters

Abstract

This article reviews the fundamentals of multilevel multiphase neutral‐point‐clampedDC–ACpower converters. These converters are configured with one or more legs and a commonDC‐link. Each leg is functionally equivalent to a single‐pole multiple‐throw switch (n ≥ 3 positions) and it is implemented with a combination of only power semiconductor devices. The main leg topologies are initially presented, both active(transistor) clamped and passive(diode) clamped, for any number of levels. The leg switching states enabling all possible leg positions are subsequently discussed. Then, the set of all possible converter switching states and their standard representation in the converter space vector diagram is systematically derived, starting from the simplest converter (single‐phase single‐leg) up to the most complex converter with an arbitrary number of phases. The space vector diagram is illustrated for three‐, four‐, andn‐levels in the usual single‐phase and three‐phase cases. Once the converter states have been characterized, the most common converter control approaches are introduced on the basis of the space vector diagram, including space vector control, space vector modulation, programmed pulse width modulation, hysteresis control, and predictive control. These control strategies are illustrated in simple and conventionalDC–ACconverter configurations. Finally, the article discusses theDC‐link capacitor voltage balance problem, which is inherent to these topologies whenever theDC‐link is configured with a capacitive voltage divider. The basics of the different solutions to guarantee the balancing are presented, both through the inclusion of additional hardware and through the application of a suitable converter control strategy.

FPGA-Based Controller for a Permanent-Magnet Synchronous Motor Drive Based on a Four-Level Active-Clamped DC-AC Converter

“…To the best of the authors' knowledge, for the first time, a complete controller for a four-level converter of the NPC converter family [4], operating as a motor drive and including DC-link voltage balancing control, is fully-embedded into an FPGA. In addition, the controller implementation has been optimized to save FPGA resources and also to take full advantage of the FPGA potential performance capabilities.…”

“…A ROM is used to calculate the function m = 0.98/sin (θ + 60 • ). Module M F3 calculates the values of d 1 , d 4 and d 5 , according to Equation (4). Two ROMs are used to calculate d 1 and d 4 .…”

“…the authors propose to use a MAC converter to drive a permanent-magnet synchronous motor (PMSM). The MAC topology belongs to the family of neutral-point clamped (NPC) topologies [4]. In this family of topologies, one typical configuration consists of connecting a set of capacitors in series to passively generate the multiple voltage levels, see Figure 2.…”

“…This modulation strategy enables to minimize the size of the capacitors, which leads to a higher power density. Although the applied modulation scheme is intended to preserve the balance of the DC-link capacitor voltages in every switching cycle, it is necessary to apply an additional control loop to guarantee a tight voltage balancing, since non-idealities lead to DC-link The MAC topology belongs to the family of neutral-point clamped (NPC) topologies [4]. In this family of topologies, one typical configuration consists of connecting a set of capacitors in series to passively generate the multiple voltage levels, see Figure 2.…”

“…This modulation is implemented here together with the VBC to drive a PMSM, demonstrating the feasibility of the proposed controller for motor-drive applications. Additionally, a four-level converter is used, in which the capacitor voltage balancing is much more challenging than in a three-level converter since some of the capacitor voltages may collapse [4]. voltage unbalancing.…”