Neutron, 64 MeV Proton, Thermal Neutron and Alpha Single-Event Upset Characterization of Xilinx 20nm UltraScale Kintex FPGA

Maillard, Pierre; Hart, Michael J.; Barton, J. C.; Jain, Praful; Karp, James

doi:10.1109/redw.2015.7336723

Cited by 27 publications

(7 citation statements)

References 5 publications

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“…In [7], the authors investigate the thermal neutron sensitivity of a 40 nm SRAM in which they present a residual source of 10 B from doping in silicon. A characterization of SEUs in Xilinx 20 nm UltraScale Kintex FPGA is presented in [13], resulting in a cross-section comparison on devices with and without a technique to mitigate the effects under thermal neutron irradiation. Also, as presented in [14], the contribution of thermal-neutron-induced soft-error rate (SER) in 16-nm bulk FinFET flip-flops can be comparable with the high-energy-neutron-induced SER, showing variations for different flip-flops designs, owing to different 10 B contamination and different critical charge values.…”

Section: Introductionmentioning

confidence: 99%

Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM

Luza

Söderström

Puchner

et al. 2020

2020 15th Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Section: Introductionmentioning

confidence: 99%

Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM

Luza

Söderström

Puchner

et al. 2020

2020 15th Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…The SEU cross section for the Kintex-7 configuration memory has been studied through proton and neutron irradiations in the past: by reading back the configuration-memory bitstream after irradiation with 180-MeV [5], 105-MeV [7], and 64-MeV protons [29] and TSL neutrons [5], by using the Xilinx SEM core during irradiation with 35-MeV protons [30], by using custom error detection and correction firmware during irradiation with 30-MeV protons [31], and by using an external scrubber providing error detection and correction during irradiation with 62-MeV protons [32]. These experiments were performed on different devices than in the present work, using FPGA part numbers XCK70T [30], [32] and XCK325T [5], [7], [29], [31] (compared to XCK160T used in the present work).…”

Section: Discussionmentioning

confidence: 99%

Proton- and Neutron-Induced Single-Event Upsets in FPGAs for the PANDA Experiment

Preston

Calén

Johansson

et al. 2020

IEEE Trans. Nucl. Sci.

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Single-event upsets (SEUs) affecting the configuration memory of a 28-nm field-programmable gate array (FPGA) have been studied through experiments and Monte Carlo modeling. This FPGA will be used in the front-end electronics of the electromagnetic calorimeter in PANDA (Antiproton Annihilation at Darmstadt), an upcoming hadron-physics experiment. Results from proton and neutron irradiations of the FPGA are presented and shown to be in agreement with previous experimental results. To estimate the mean time between SEUs during operation of PANDA, a Geant4-based Monte Carlo model of the phenomenon has been used. This model describes the energy deposition by particles in a silicon volume, the subsequent drift and diffusion of charges in the FPGA memory cell, and the eventual collection of charges in the sensitive regions of the cell. The values of the two free parameters of the model, the sensitive volume side d = 87 nm and the critical charge Q crit = 0.23 fC, were determined by fitting the model to the experimental data. The results of the model agree well with both the proton and neutron data and are also shown to correctly predict the cross sections for upsets induced by other particles. The modelpredicted energy dependence of the cross section for neutroninduced upsets has been used to estimate the rate of SEUs during initial operation of PANDA. At a luminosity of 1 • 10 31 cm −2 s −1 , the predicted mean time between upsets (MTBU) is between 120 and 170 h per FPGA, depending on the beam momentum.

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“…We ran benchmark and validation tests to determine the processing throughput and latency using a Xilinx KU060 FPGA [42]. Our choice of an XCKU060 FPGA was based on our initial estimate of the required resources as well as its ongoing path to spaceflight qualification [43,44]. This is the same FPGA chosen for the prototype version of SALi [11].…”

Section: Data Processing Time With a Xcku060 Fpgamentioning

confidence: 99%

Small PN-Code Lidar for Asteroid and Comet Missions—Receiver Processing and Performance Simulations

et al. 2021

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Space missions to study small solar system bodies, such as asteroids and comet cores, are enhanced by lidar that can provide global mapping and serve as navigation sensors for landing and surface sampling. A small swath-mapping lidar using a fiber laser modulated by pseudo-noise (PN) codes is well-suited to small space missions and can provide contiguous measurements of surface topography with < 10 cm precision. Here, we report the design and simulation of receiver signal processing of such a lidar using the small all-range lidar (SALi) as a design example. We simulated its performance in measuring the lidar range and surface reflectance by using instrument and target parameters, noise sources, and the receiver correlation processing method under various conditions. In single-beam Reconnaissance mode, the simulation predicted a maximum range of 440 km under sunlit conditions with a range precision as small as 8 cm. In its multi-pixel Mapping mode, the lidar can provide measurements out to 110 km with range precision of 5 cm. The effects of Doppler shift were quantified. From these results, we discuss the need for Doppler compensation via the receiver clock rate. We also describe a novel reflectance measurement method using active laser control, which allows the receiver to use simple comparators for analog-to-digital conversion. This method was simulated with surface reflectance values from 4% to 36% resulting in an RMS precision of 3% and a bias of 1% of the surface reflectance. We also performed an orbital ranging simulation using a shape model of 101955 Bennu for target surface elevation. The range residuals showed a sub-mm bias with a standard deviation of 5 cm. We implemented the receiver processor design on a Xilinx Ultrascale field-programmable gate array (FPGA). It was able to process received signals and retrieve accurate ranges at a single-channel measurement rate of 3050 Hz with a latency of 1.07 milliseconds.

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Neutron, 64 MeV Proton, Thermal Neutron and Alpha Single-Event Upset Characterization of Xilinx 20nm UltraScale Kintex FPGA

Cited by 27 publications

References 5 publications

Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM

Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM

Proton- and Neutron-Induced Single-Event Upsets in FPGAs for the PANDA Experiment

Small PN-Code Lidar for Asteroid and Comet Missions—Receiver Processing and Performance Simulations

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