Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

Loveless, T. D.; Jagannathan, S.; Reece, Trey; Chetia, J; Bhuva, B. L.; McCurdy, Mike; Massengill, L.W.; Wen, S.-J.; Wong, Richard; Rennie, D.

doi:10.1109/tns.2011.2123918

Cited by 111 publications

(30 citation statements)

References 12 publications

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“…These hardened latches have proved to be effective RHBD latches when only one node collects charge [2]. However, multiple nodes charge collection will attenuate the hardening performance of these latches [7,9].…”

Section: Challenges For Traditional Redundancy Based Hardened Latchesmentioning

confidence: 99%

“…Related work has pointed out that the performance of DICE to mitigate SEU was largely decreased due to charge sharing [9,14]. Other redundancy based latches also face this challenge [3,4].…”

Section: Challenges For Traditional Redundancy Based Hardened Latchesmentioning

confidence: 99%

“…Charge sharing is becoming serious in advanced technologies [5,6,7,8]. This is a great challenge for the redundancy based latch [9,10,11].…”

Section: Introductionmentioning

confidence: 99%

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Multiple nodes upset tolerance DICE latch based on on-state transistor

Zhang

Qin

2014

IEICE Electron. Express

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Section: Challenges For Traditional Redundancy Based Hardened Latchesmentioning

confidence: 99%

Section: Challenges For Traditional Redundancy Based Hardened Latchesmentioning

confidence: 99%

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Multiple nodes upset tolerance DICE latch based on on-state transistor

Zhang

Qin

2014

IEICE Electron. Express

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“…One of the important storage elements that is used in the shift register chip is a flip-flop (FF) [10,11]. To design a low power and high-performance shift register, attention must be given in designing high-performance FFs [12].…”

Section: Introductionmentioning

confidence: 99%

Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

et al. 2016

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Abstract:The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in -parallel out (PIPO) and serial in -serial out (SISO) shift register respectively covering 22 µm 2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

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“…The specific error-correcting code was proposed in paper [5] for protecting CAM from multiple cell upsets under impacts of single nuclear particles. The design using replacement of a 6-transistor memory cell on the DICE (Dual Interlocked Storage Cell) with the traditional topology does not solve the problem of the RAM or CAM reliability enhancement [6]. The reduction of distances between pairs of mutually sensitive nodes of the standard DICE cell led to the loss of the resistance to impacts of single nuclear particles [6], [7].…”

mentioning

confidence: 99%

Comparison elements on STG DICE cell for content-addressable memory and simulation of single-event transients

Stenin

Antonyuk

2017

Telfor

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-Comparison elements on base the STG DICE cell and the logical element "Exclusive OR" for a contentaddressable memory were designed and simulated. The comparison element contains two identical joint groups of transistors that are spaced on the chip by the distance of four micrometers, so the loss of data in STG DICE cell practically excluded. On the characteristics of the new 65-nm CMOS comparison element, we predict the hardness of these item to single event rate (SER) more to hundred times compared to elements on 6-transistors cells and the standard DICE cell with distances 0.5-0.6 μm between mutually sensitive nodes.

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Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

Cited by 111 publications

References 12 publications

Multiple nodes upset tolerance DICE latch based on on-state transistor

Multiple nodes upset tolerance DICE latch based on on-state transistor

Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

Comparison elements on STG DICE cell for content-addressable memory and simulation of single-event transients

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