Neutron radiation test of graphic processing units

Rech, Paolo; Aguiar, C.; Ferreira, Ronaldo Rodrigues; Frost, Christopher; Carro, Luigi

doi:10.1109/iolts.2012.6313841

Cited by 19 publications

(4 citation statements)

References 18 publications

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“…A SEE may occur when an outside disturber, such as radiation particle from space, hits the device causing wrong behavior in the circuit. The energy for a particle to trigger SEE decreases along with the transistor size, while considering SEEs induced by radiation particles at sea level have been reported more than a few years [61], it is mandatory to apply fault tolerant strategies to improve reliability of the system when designing safety-and mission-critical applications. Two main effects among SEEs considered in this work are Single Event Upset (SEU) and Single Event Transient (SET).…”

Section: Single Event Effects On Fpgasmentioning

confidence: 99%

Fault tolerant electronic system design

Sterpone

2017

2017 IEEE International Test Conference (ITC)

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Section: Single Event Effects On Fpgasmentioning

confidence: 99%

Fault tolerant electronic system design

Sterpone

2017

2017 IEEE International Test Conference (ITC)

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“…Wang et al [2004] show that simulator-based studies miss many circuit-level phenomena, which in the CPU case mask most transient faults, resulting in "fewer than 15% of single bit corruptions in processor state resulting in software visible errors." Our goal is to study this for GPUs, complementing simulatorbased studies and hardware measurement studies [Rech et al 2012], which cannot provide fine-grained susceptibility information.…”

Section: Validation/calibration Of Simulator-based Characterization Omentioning

confidence: 99%

“…However, RTL-level implementations and low-level detailed microarchitecture specification are lacking. As discussed by others [Chen 2009;Jeon and Annavaram 2012;Menon et al 2012;Rech et al 2012;Tan et al 2011], GPUs are beginning to see many of the same technology and device reliability challenges that have driven some of the aforementioned RTL-based CPU research topics. The lack of an RTL-level implementation of a GPU hampers similar efforts in the GPU space.…”

Section: Introductionmentioning

confidence: 99%

Enabling GPGPU Low-Level Hardware Explorations with MIAOW

Balasubramanian

Gangadhar

Guo

et al. 2015

ACM Trans. Archit. Code Optim.

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Graphic processing unit (GPU)-based general-purpose computing is developing as a viable alternative to CPU-based computing in many domains. Today's tools for GPU analysis include simulators like GPGPUSim, Multi2Sim, and Barra. While useful for modeling first-order effects, these tools do not provide a detailed view of GPU microarchitecture and physical design. Further, as GPGPU research evolves, design ideas and modifications demand detailed estimates of impact on overall area and power. Fueled by this need, we introduce MIAOW (Many-core Integrated Accelerator Of Wisconsin), an open-source RTL implementation of the AMD Southern Islands GPGPU ISA, capable of running unmodified OpenCL-based applications. We present our design motivated by our goals to create a realistic, flexible, OpenCL-compatible GPGPU, capable of emulating a full system. We first explore if MIAOW is realistic and then use four case studies to show that MIAOW enables the following: physical design perspective to "traditional" microarchitecture, new types of research exploration, and validation/calibration of simulator-based characterization of hardware. The findings and ideas are contributions in their own right, in addition to MIAOW's utility as a tool for others' research.

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“…Recently, GPGPUs have been evaluated using spallation neutron sources that provide the user with an atmospheric-like spectrum. A preliminary experimental setup for the execution of neutron radiation test of a GPGPU has been proposed in [10]. The authors describe a low-cost but effective setup providing some guidelines on how to test GPGPUs, focusing on the constraints imposed by the radiation source and the device connections with the host computer controlling the experiment.…”

Section: Related Workmentioning

confidence: 99%

Reliability Evaluation of Embedded GPGPUs for Safety Critical Applications

Sabena

Sterpone

Carro

et al. 2014

IEEE Trans. Nucl. Sci.

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Thanks to the capability of efficiently executing massive computations in parallel, general purpose graphic processing units (GPGPUs) have begun to be preferred to CPUs for several parallel applications in different domains. Two are the most relevant fields in which, recently, GPGPUs have begun to be employed: high performance computing (HPC) and embedded systems. The reliability requirements are different in these two applications domain. In order to be employed in safety-critical applications, GPGPUs for embedded systems must be qualified as reliable. In this paper, we analyze through neutron irradiation typical parallel algorithms for embedded GPGPUs and we evaluate their reliability. We analyze how caches and threads distributions affect the GPGPU reliability. The data have been acquired through neutron test experiments, performed at the VESUVIO neutron facility at ISIS. The obtained experimental results show that, if the L1 cache of the considered GPGPU is disabled, the algorithm execution is most reliable. Moreover, it is demonstrated that during a FFT execution most errors appear in the stages in which the GPGPU is completely loaded as the number of instantiated parallel tasks is higher.

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Neutron radiation test of graphic processing units

Cited by 19 publications

References 18 publications

Fault tolerant electronic system design

Fault tolerant electronic system design

Enabling GPGPU Low-Level Hardware Explorations with MIAOW

Reliability Evaluation of Embedded GPGPUs for Safety Critical Applications

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