New activity-driven clock tree design methodology for low power clock gating

Lin, Chen-Hsien; Huang, Shih-Hsu; Jian, Jia-Hong; Chen, Xin-Jia

doi:10.1109/isne.2017.7968741

Cited by 6 publications

(2 citation statements)

References 5 publications

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“…Chan et al [17] proposed a linear programming methodology to minimize power consumption, wire length, and timing slew simultaneously. Lin et al [18] proposed an activity-driven clock tree design methodology, including a new tree structure and a corresponding design flow. Cheng et al [19] proposed a skew-window-based methodology to reduce the total hardware cost of ADBs and clock gates simultaneously.…”

Section: Clock Treementioning

confidence: 99%

Cross-Mesh Clock Network Synthesis

et al. 2023

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In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh architecture is easier to satisfy the clock skew constraint, but it usually has much more power consumption. Therefore, a hybrid clock network architecture that combines both the clock tree and clock mesh seems to be a promising solution. In a normal hybrid mesh/tree structure, a driving buffer is placed in the intersection of mesh lines. In this paper, we propose a novel cross-mesh architecture, and we distribute the buffers to balance the overall switching capacitance, reducing the number of registers connected to a subtree, and the load capacitance of a buffer. With the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating, register clustering, and load balancing techniques to optimize clock skew and load capacitance simultaneously. The proposed methodology has four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our cross-mesh architecture has high tolerance for process variation, and is robust in all the operation modes. Comparing it to the uniform mesh architecture, our methodology and algorithms reduce 28.9% of load capacitance and 80.4% of clock skew on average. Compared to the non-uniform mesh architecture, we also reduce capacitance by 22.4% and skew by 76.7% on average. This illustrates that we can obtain a feasible solution effectively and improve both power consumption and clock skew simultaneously.

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Section: Clock Treementioning

confidence: 99%

Cross-Mesh Clock Network Synthesis

et al. 2023

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“…Research [15] proposed a linear programming methodology to minimize power consumption, wire length, and timing slew simultaneously. Research [16] proposed an activitydriven clock tree design methodology, including a new tree structure and a corresponding design flow. Research [17] proposed a skew-window-based methodology to reduce the total hardware cost of ADBs and clock gates simultaneously.…”

Section: Clock Treementioning

confidence: 99%

Cross-Mesh Clock Network Synthesis

Cheng¹,

Yeh²,

Kao³

et al. 2023

Preprint

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In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. To achieve this target, a hybrid clock network architecture that combines both clock tree and clock mesh seems to be a promising solution. In this paper, we propose a novel clock mesh architecture – cross-mesh, with the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating and register clustering techniques to further reduce dynamic power consumption. The proposed algorithms have four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our methodology and algorithms get feasible solution effectively and improve both power consumption and clock skew simultaneously.

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Design of Sequential Circuit Using Data Driven Clock Gating and Multibit Flip-Flop Integration

Arunraj¹,

Hiremath²

2019

2019 3rd International Conference on Electronics, Communication and Aerospace Technology (ICECA)

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New activity-driven clock tree design methodology for low power clock gating

Cited by 6 publications

References 5 publications

Cross-Mesh Clock Network Synthesis

Cross-Mesh Clock Network Synthesis

Cross-Mesh Clock Network Synthesis

Design of Sequential Circuit Using Data Driven Clock Gating and Multibit Flip-Flop Integration

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