New Algorithm for Signed Integer Comparison in $\{2^{n+k},2^{n}-1,2^{n}+1,2^{n\pm 1}-1\}$ and Its Efficient Hardware Implementation

Kumar, Sachin; Chang, Chip-Hong; Tay, Thian Fatt

doi:10.1109/tcsi.2016.2561718

Cited by 13 publications

(10 citation statements)

References 24 publications

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“…Also, modeling was done to compare the proposed moduli sets with balanced RNS moduli sets. The following types of moduli sets were chosen for the simulation: {2 n − 1, 2 n , 2 n + 1} [29,30], 2 n − 1, 2 n+k , 2 n + 1 [31], 2 n − 1, 2 n , 2 n + 1, 2 n+1 + 1 [34], 2 n − 1, 2 n + 1, 2 n±1 − 1, 2 n+k [35]. All simulated circuits were described in very high speed integrated circuit (VHSIC) hardware description language (VHDL).…”

Section: Resultsmentioning

confidence: 99%

“…For example, the sorting network uses a large number of comparators and is one of the key elements in electronic finance data management systems, digital computers and communication systems [39]. Due to the excessive number of magnitude comparisons required in sorting a large pool of data, the speed of the magnitude comparator determines the overall delay of the sorting process [35].…”

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confidence: 99%

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Construction of Residue Number System Using Hardware Efficient Diagonal Function

et al. 2019

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The residue number system (RNS) is a non-positional number system that allows one to perform addition and multiplication operations fast and in parallel. However, because the RNS is a non-positional number system, magnitude comparison of numbers in RNS form is impossible, so a division operation and an operation of reverse conversion into a positional form containing magnitude comparison operations are impossible too. Therefore, RNS has disadvantages in that some operations in RNS, such as reverse conversion into positional form, magnitude comparison, and division of numbers are problematic. One of the approaches to solve this problem is using the diagonal function (DF). In this paper, we propose a method of RNS construction with a convenient form of DF, which leads to the calculations modulo 2 n , 2 n − 1 or 2 n + 1 and allows us to design efficient hardware implementations. We constructed a hardware simulation of magnitude comparison and reverse conversion into a positional form using RNS with different moduli sets constructed by our proposed method, and used different approaches to perform magnitude comparison and reverse conversion: DF, Chinese remainder theorem (CRT) and CRT with fractional values (CRTf). Hardware modeling was performed on Xilinx Artix 7 xc7a200tfbg484-2 in Vivado 2016.3 and the strategy of synthesis was highly area optimized. The hardware simulation of magnitude comparison shows that, for three moduli, the proposed method allows us to reduce hardware resources by 5.98-49.72% in comparison with known methods. For the four moduli, the proposed method reduces delay by 4.92-21.95% and hardware costs by twice as much by comparison to known methods. A comparison of simulation results from the proposed moduli sets and balanced moduli sets shows that the use of these proposed moduli sets allows up to twice the reduction in circuit delay, although, in several cases, it requires more hardware resources than balanced moduli sets. such as field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). All these attractive features increase interest to RNS in the areas where large amounts of computation are needed. The applications of RNS are digital signal processing [2][3][4], cryptography [5][6][7], digital image processing [8], cloud computing [9], Internet of Things [10] and others. In [11], the authors propose a technique to estimate real-valued numbers by means of the Chinese remainder theorem (CRT), employing for this goal a Kroenecker based M-Estimation, to improve robustness. A new method based on the Chinese remainder theorem (CRT) is proposed for absolute position computation in [12]. This has advantages in terms of hardware and flexibility because it does not use memory. The authors of [13] offer to use RNS to improve the performance of the convolutional neural network developed for pattern recognition tasks. Reference [14] describes the method of construction for finite impulse response filers using RNS.However, the limitations of RNS include some operations such a...

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Section: Resultsmentioning

confidence: 99%

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confidence: 99%

Construction of Residue Number System Using Hardware Efficient Diagonal Function

et al. 2019

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“…Residue number systems are remarkable for fast summation, subtraction, and multiplication, which explains major interest in these systems for the applications requiring large volumes of calculations. However, some operations (modulo reduction, comparison and division of numbers) are very complicated in RNSs [14,15]. The development of more efficient algorithms for comparison, sign detection, and division would open up new applications of RNSs [16].…”

Section: Of 17mentioning

confidence: 99%

A High-Speed Division Algorithm for Modular Numbers Based on the Chinese Remainder Theorem with Fractions and Its Hardware Implementation

et al. 2019

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In this paper, a new simplified iterative division algorithm for modular numbers that is optimized on the basis of the Chinese remainder theorem (CRT) with fractions is developed. It requires less computational resources than the CRT with integers and mixed radix number systems (MRNS). The main idea of the algorithm is (a) to transform the residual representation of the dividend and divisor into a weighted fixed-point code and (b) to find the higher power of 2 in the divisor written in a residue number system (RNS). This information is acquired using the CRT with fractions: higher power is defined by the number of zeros standing before the first significant digit. All intermediate calculations of the algorithm involve the operations of right shift and subtraction, which explains its good performance. Due to the abovementioned techniques, the algorithm has higher speed and consumes less computational resources, thereby being more appropriate for the multidigit division of modular numbers than the algorithms described earlier. The new algorithm suggested in this paper has O (log2 Q) iterations, where Q is the quotient. For multidigit numbers, its modular division complexity is Q(N), where N denotes the number of bits in a certain fraction required to restore the number by remainders. Since the number N is written in a weighed system, the subtraction-based comparison runs very fast. Hence, this algorithm might be the best currently available.

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“…For all such applications, RNS provides outstanding performance with high computational speed, lesser area, and low power dissipation, which are the major objective of today's real-time processors. Additionally, the reverse conversion [15][16][17], division [18][19], scalar [20], magnitude comparison [21][22], overflow detection [23][24][25] and sign detection [26][27][28][29][30][31][32][33][34][35][36][37] are also the essential operation of RNS. These operations are not easy to perform in RNS.…”

Section: Introductionmentioning

confidence: 99%

“…Recently numerous efforts have been made in the area of sign detector, which presents different architectures of sign detector for different moduli sets. Some of them are designed for universal moduli set [26][27][28][29], 3-moduli set [30][31][32][33][34] and extended moduli set [35][36][37]. The 3-moduli set {2 n -1, 2 n , 2 n +1} is very popular as this results in less complex arithmetic circuits due to the availability of the number of modulo properties.…”

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confidence: 99%

Design and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}

Kumar

Mishra

2021

IJEECS

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Magnitude comparison, sign detection and overflow detection are essential operations of residue number system (RNS) that are used in digital signal processing (DSP) applications. Moreover, sign detection attracts significant attention in RNS as it can also be used in division and magnitude comparison operations. However, these operations are not easy to perform in RNS. So, there is a need arise to propose a computationally advanced RNS based sign detector. This paper presents an area and power-efficient sign detection circuit for modulo {2n - 1, 2n, 2n + 1} using mixed radix conversion technique. The proposed sign detector is constructed using a carry save adder (CSA), a modified parallel prefix adder and a carry-generation circuit. Based on the synthesized results using synopsys design compiler, the introduced design offers better results in terms of the area required and power consumption. Although, the speed will remain the same when compared to the recent sign detectors for the same moduli set.

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New Algorithm for Signed Integer Comparison in $\{2^{n+k},2^{n}-1,2^{n}+1,2^{n\pm 1}-1\}$ and Its Efficient Hardware Implementation

Cited by 13 publications

References 24 publications

Construction of Residue Number System Using Hardware Efficient Diagonal Function

Construction of Residue Number System Using Hardware Efficient Diagonal Function

A High-Speed Division Algorithm for Modular Numbers Based on the Chinese Remainder Theorem with Fractions and Its Hardware Implementation

Design and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}

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