New algorithms for minimizing the longest wire length during circuit compaction

Abstract

Abslracl. Consider the problem of performing onc-dimensionol circuit~mpac[ion for a layout containing nh horizontal wires and n layout cells. We present Dew and efficient cons[raint-graph-bas~algorithms lor generating acompacled layout in which eilhcnbelenglh oflhc longestwircsor a user-specil1ed uadcofffunction between the layoul widlh Bnd Ihe longesl wire lenglh is minimized. Bolli algorithms have. an O(nh ' 11 logn) running time. The concept employed by our a1gorilhms is that of assigning speeds to the layoul eells. Speeds are computed by performing path computations in subgraphs of the conslraint graphs. A compacled layoul is generated over a number of iterations. with each ilemtion first delermining speeds and then moving the layout elements 10 the right according 10 die computed speeds. Each ilernlion produces a better layout and after at most n • nh ilerations die finallay(lut is produced.