New approaches for in-system debug of behaviorally-synthesized FPGA circuits

Monson, Joshua S.; Hutchings, Brad

doi:10.1109/fpl.2014.6927495

Cited by 25 publications

(25 citation statements)

References 11 publications

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“…In their work, Monson and Hutchings [9] propose the use of Event Observability Ports (EOP) to provide a structure for source-to-hardware correspondence which could be added to either the RTL code (for simulation) or synthesis netlist (for in-system debugging). In practice, an EOP is a top-level RTL port that corresponds to the output of a specific expression or statement in the original source.…”

Section: Event Observability Portsmentioning

confidence: 99%

Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs

Monson

Hutchings

2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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This paper proposes a method for extending source-level visibility into the RTL of an HLS-generated design using automated source-level transformations. Using our method, source-level visibility can be extended into co-simulation, insystem simulation, and hardware execution of any HLS tool that provides the ability to infer top-level ports. Experimental results show the feasibility of our method in situations where visibility needs to be added without modifying the timing, latency, or throughput of the design.

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Section: Event Observability Portsmentioning

confidence: 99%

Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs

Monson

Hutchings

2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…[7], for example, shows a technique for maximizing the observable events with low area overhead. The tracing circuits described by the authors can be inserted with small modifications and they can be optimized using high-level knowledge of the Control Flow Graphs and State Transition Graphs used for HLS.…”

Section: B Recent Advances In Debugging Hls-generated Circuitsmentioning

confidence: 99%

Trace-based automated logical debugging for high-level synthesis generated circuits

Fezzardi

Castellana

Ferrandi

2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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Abstract-In this paper we present an approach for debugging hardware designs generated by High-Level Synthesis (HLS), relieving users from the burden of identifying the signals to trace and from the error-prone task of manually checking the traces. The necessary steps are performed after HLS, independently of it and without affecting the synthesized design. For this reason our methodology should be easily adaptable to any HLS tools.The proposed approach makes full use of HLS compile time informations. The executions of the simulated design and the original C program can be compared, checking if there are discrepancies between values of C variables and signals in the design. The detection is completely automated, that is, it does not need any input but the program itself and the user does not have to know anything about the overall compilation process. The design can be validated on a given set of test cases and the discrepancies are detected by the tool. Relationships between the original high-level source code and the generated HDL are kept by the compiler and shown to the user. The granularity of such discrepancy analysis is per-operation and it includes the temporary variables inserted by the compiler. As a consequence the design can be debugged as is, with no restrictions on optimizations available during HLS.We show how this methodology can be used to identify different kind of bugs: 1) introduced by the HLS tool used for the synthesis; 2) introduced using buggy libraries of hardware components for HLS; 3) undefined behavior bugs in the original high-level source code.

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“…Recent academic work has started to tackle the problem of providing source-level in-situ debugging for HLS generated circuits [8]- [10]. This task is challenging for two reasons: (1) the source code may undergo many optimizing transformations when synthesized from the software domain to hardware, and (2) limited I/O ports make it difficult to observe the many internals signals of executing hardware circuits.…”

Section: Introductionmentioning

confidence: 99%

“…One problematic optimization is that variables are frequently optimized out of memory and replaced with registers within the datapath. Our technique leverages the approach first presented in [10], using the information within the HLS schedule to determine which signals are relevant to trace each cycle, and efficiently record the behaviour of these signals in on-chip memory. We explore different scheduling methods to balance the number of signals that must be recorded each cycle, increasing the utilization of the trace memory.…”

Section: Introductionmentioning

confidence: 99%

Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs

Goeders

Wilton

2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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High-level synthesis (HLS) for FPGA designs has received considerable attention in recent years. To make this design methodology mainstream, improved debugging technologies are essential. Ideally, a user should be able to debug their design using the original source code, without detailed knowledge of the underlying hardware, while the circuit executes in-situ. Although recent work has made progress toward this goal, existing solutions lack a full system for obtaining visibility into circuits that have been heavily optimized by the compiler. HLS compilers typically perform many optimizations, including moving variable values out of memories and into registers distributed throughout the design. Debugging such circuits typically requires either understanding the hardware and probing the appropriate RTLlevel registers, or ignoring these variables while debugging the design, neither of which is desirable.In this work we present a new signal-tracing technique, specifically designed for circuits that have been optimized by an HLS tool. We build on past work which extracts information from the HLS process to determine which signals are relevant to record each cycle. We automatically embed circuitry which dynamically selects the relevant signals, cycle-by-cycle, and records them into on-chip memories. In addition, we explore techniques to balance tracing between cycles to further improve memory efficiency. For each 100Kb of memory allocated to trace buffers, our technique can, on average, record and replay 4322 lines of source code, versus 141 lines using conventional tracing methods.

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New approaches for in-system debug of behaviorally-synthesized FPGA circuits

Cited by 25 publications

References 11 publications

Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs

Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs

Trace-based automated logical debugging for high-level synthesis generated circuits

Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs

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