New categories of Safe Faults in a processor-based Embedded System

Gürsoy, Cemil Cem; Jenihhin, Maksim; Oyeniran, Adeboye Stephen; Piumatti, D.; Raik, Jaan; Reorda, M. Sonza; Ubar, Raimund

doi:10.1109/ddecs.2019.8724642

Cited by 4 publications

(3 citation statements)

References 14 publications

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“…As our experimental results proved [7,8], UFs represent a significant percentage of the faults. This may be due to different reasons, such as the used encoding style, the constraints adopted when assembling the whole design, etc.…”

Section: Untestable Faultssupporting

confidence: 65%

Untestable faults identification in GPGPUs for safety-critical applications

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Silva

Hamdioui

et al. 2019

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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1-Nowadays, General Purpose Graphics Processing Units (GPGPUs) devices are considered as promising solutions for high-performance safety-critical applications, such as those in the automotive field. However, their adoption requires solutions to effectively detect faults arising in the device during the operative life. Hence, effective in-field test solutions are required to guarantee high-reliability levels. In this paper, we leverage the results of Software-Based Self-Test (SBST) based approaches for GPGPUs by deploying new techniques for automating the identification of untestable faults (UF). Our methodology has achieved fault coverage of 82.8% when applied to an open-source implementation of the NVIDIA G80 GPU architecture. The proposed approach combining SBSTs and UFs identification appears as an effective solution for the reliability analysis of GPGPUs.

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Section: Untestable Faultssupporting

confidence: 65%

Untestable faults identification in GPGPUs for safety-critical applications

Condia

Silva

Hamdioui

et al. 2019

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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“…Examples of this approach are [22][23][24], which aim at identifying untestable faults in sequential circuits. We note that untestable faults are, by definition, safe faults [25]. In addition, Refs.…”

Section: Related Workmentioning

confidence: 96%

“…In addition, Refs. [6,25,26] resort to ATPG to identify application-dependent safe faults, which is the same target of the work described in this paper. Even though these works can identify safe faults using the ATPG, they still have a manual part in their flow, i.e., they are semi-automated.…”

Section: Related Workmentioning

confidence: 99%

Automated Identification of Application-Dependent Safe Faults in Automotive Systems-on-a-Chips

et al. 2022

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ISO 26262 requires classifying random hardware faults based on their effects (safe, detected, or undetected) within integrated circuits used in automobiles. In general, this classification is addressed using expert judgment and a combination of tools. However, the growth of integrated circuit complexity creates a huge fault space; hence, this form of fault classification is error prone and time consuming. Therefore, an automated and systematic approach is needed to target hardware fault classification in automotive systems on chips (SoCs), considering the application software. This work focuses on identifying safe faults: the proposed approach utilizes coverage analysis to identify candidate safe faults considering all the constraints coming from the application. Then, the behavior of the application software is modeled so that we can resort to a formal analysis tool. The proposed technique is evaluated on the AutoSoC benchmark running a cruise control application. Resorting to our approach, we could classify 20%, 11%, and 13% of all faults in the central processing unit (CPU), universal asynchronous receiver–transmitter (UART), and controller area network (CAN) as safe faults, respectively. We also show that this classification can increase the diagnostic coverage of software test libraries targeting the CPU and CAN modules by 4% to 6%, increasing the achieved testable fault coverage.

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