New Current-Mode Integrated Ternary Min/Max Circuits without Constant Independent Current Sources

Abstract

Novel designs of current-mode Ternary minimum (AND) and maximum (OR) are proposed in this paper based on Carbon NanoTube Field Effect Transistors (CNTFET). First, these Ternary operators are designed separately. Then, they are combined together in order to generate both outputs concurrently in an integrated design. This integration results in the elimination of common parts when both functions are required at the same time. The third proposed current-mode integrated circuit generates both ternary operators with the usage of only 30 transistors. The new designs are composed of three main parts: (1) the part which converts current to voltage; (2) threshold detectors; and (3) the parallel paths through which the output current flows. Unlike the previously presented structure, there is no need for any constant current source within the new designs. This elimination leads to less static power dissipation. The second proposed current-mode segregated Ternary minimum operates 43% faster and consumes 40% less power in comparison with a previously presented structure.

New Current-Mode Ternary Full Adder Circuits Based on Carbon Nanotube Field Effect Transistor Technology

“…The output current is mirrored in CML to be connected to the fan-out circuits. 29 the lack of active current path, while C out would be 16 A because of adding two current flow paths.…”

“…29 In case being output currents are mirrored to the new branches, rather than a direct connection, (Fig. 9).…”

“…9). 29 Hence, simulation procedures are recreated twice more to investigation mentioned capability as follow: First, only one output load transistor is added to the both output nodes of the proposed circuits. Then, four copies of the output current are included for outputs in the examination.…”

“…In some fuzzy circuit, this disability may cause the incensement of signal offset and propagate it within the entire system, resulting in information loss. 29 Sum(Next Cell) = Sum ⊕ C out ⊕ C out = Sum…”

High-Performance CML approximate full adders for image processing application of laplace transform

“…In the present study, CML is selected for the implementation of the proposed approximate adders. This logic style has many advantages such as low noise sensitivity because of the constant flow of current (Delican and Yildirim, 2011), high speed (Badel et al , 2019), elimination of sign bit by using the direction of current as an interpretation of sign (Jamshidi and Fazeli, 2018), linear addition of current values without active devices (Yanushkevich, 2004), insignificant effects of fan-out circuits by using current mirrors without intensifying output load (Moradi et al , 2015) and simple circuit alteration by employing different threshold detectors (Jiang et al , 2015). These advantages have persuaded circuit designers to use this approach for designing analog and mixed-signal logical and computational blocks (Al-Absi et al , 2013; Beyraghi and Khoei, 2015; Moradi et al , 2016; Zareei et al , 2017).…”