New current‐mode RMS‐to‐DC converters and four‐quadrant multiplier/divider based on VDTA

Petrović, Predrag

doi:10.1049/iet-cds.2019.0373

Cited by 8 publications

(4 citation statements)

References 46 publications

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“…The data that support the findings of this study are openly available in [ieee explore, Elsevier] at http://doi.org/10.1016/j.aeue.2020.153,267; 10.1109/ICTKE47035.2019.8,966,844: 10.1016/j.aeue.2020.153,360; 10.3390/electronics10111262; 10.1080/03,772,063.2020.1,830,861], reference number [1–42].…”

Section: Data Availability Statementsupporting

confidence: 53%

“…where, g mF and g mS are transconductance gains of MVDTA (two dependent transconductance gain stages). Its gains can be controlled electronically by biasing voltage or current, respectively [13]. A copy of the current i z is available at the zc-terminal (i zc ); z and zc, that is the positive and negative outputs of the first OTA section are auxiliary high impedance ports [12].…”

Section: Proposed Configuration Of Rectifier Circuitsmentioning

confidence: 99%

“…[12]

[\begin{matrix} center \\ center i_{p} \\ center i_{n} \\ center i_{z} \\ center i_{z c} \\ center i_{m} \\ center i_{x +} \\ center i_{x -} \end{matrix}] = [\begin{matrix} center \\ center 0 & center 0 & center 0 \\ center 0 & center 0 & center 0 \\ center g_{m F} & center - g_{m F} & center 0 \\ center - g_{m F} & center g_{m F} & center 0 \\ center 0 & center 0 & center 0 \\ center 0 & center 0 & center g_{m S} \\ center 0 & center 0 & center - g_{m S} \end{matrix}] [\begin{matrix} center \\ center v_{p} \\ center v_{n} \\ center v_{m} \end{matrix}]

where, g mF and g mS are transconductance gains of MVDTA (two dependent transconductance gain stages). Its gains can be controlled electronically by biasing voltage or current, respectively [13]. A copy of the current i z is available at the zc ‐terminal ( i zc ); z and zc , that is the positive and negative outputs of the first OTA section are auxiliary high impedance ports [12].…”

Section: Proposed Configuration Of Rectifier Circuitsmentioning

confidence: 99%

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New full‐wave rectifier based on modified voltage differencing transconductance amplifier

Petrović

2021

IET Circuits, Devices & Syst

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A full‐wave rectifier based on a modified voltage differencing transconductance amplifier‐MVDTA and four n‐MOS transistors (or inverting full‐wave rectifier), with no use of any passive elements is proposed in this paper. The proposed design is suitable for a low voltage and high frequency input voltage/current signal. The used MVDTA possesses certain new connections without any changes in the original circuit resources of VDTA. The proposed configuration possesses satisfactory zero crossing performance, excellent linearity, low component count―a simple and compact structure―which makes it an adequate candidate for implementation in the form of IC circuits. The amplitude‐waveform of the current/voltage rectified signal at the output of the proposed circuit can be electronically controlled by the applied bias currents. The influence of possible non‐ideality and parasitic effects was analysed, while the effects of the parasitic are only marginal due to the absence of any passive elements. To verify the validity of the presented circuits, SPICE simulations deploying 0.18 μm CMOS technology parameters and supply voltage of ±0.9 V are reported, fully consistent with the theoretical predictions. The noise and Monte Carlo analyses were also performed in order to obtain further insight into the robustness of the proposed design. The proposal is also supported by experimental results in order to confirm the workability of the proposed solution.

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Section: Data Availability Statementsupporting

confidence: 53%

Section: Proposed Configuration Of Rectifier Circuitsmentioning

confidence: 99%

“…[12]

[\begin{matrix} center \\ center i_{p} \\ center i_{n} \\ center i_{z} \\ center i_{z c} \\ center i_{m} \\ center i_{x +} \\ center i_{x -} \end{matrix}] = [\begin{matrix} center \\ center 0 & center 0 & center 0 \\ center 0 & center 0 & center 0 \\ center g_{m F} & center - g_{m F} & center 0 \\ center - g_{m F} & center g_{m F} & center 0 \\ center 0 & center 0 & center 0 \\ center 0 & center 0 & center g_{m S} \\ center 0 & center 0 & center - g_{m S} \end{matrix}] [\begin{matrix} center \\ center v_{p} \\ center v_{n} \\ center v_{m} \end{matrix}]

Section: Proposed Configuration Of Rectifier Circuitsmentioning

confidence: 99%

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New full‐wave rectifier based on modified voltage differencing transconductance amplifier

Petrović

2021

IET Circuits, Devices & Syst

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“…Gate count and adder count are high when compare to other multiplier so it occupy more area in array multiplier. In Baugh Wooley multiplier the operation speed is very much high when compared to array multiplier but delay and power consumption are very less [17][18][19][20]. Whereas in Wallace multiplier speed is high and power consumption is high when compared to Baugh Wooley multiplier.…”

Section: Limitationmentioning

confidence: 99%

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

Gavaskar¹,

Malathi²,

Ravivarma³

et al. 2021

Wireless Pers Commun

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The Multiply Accumulate (MAC) unit constructed using antiquated Vedic mathematical practice and the e ciency of the vertical and transversely of Vedic approach for multiplication, which gives a distinction in genuine cycle of Multiplier itself. Vedic-Mathematics is depend on 16-Sutras, in that Urdhva-Triyakbhyam (UT) more productive one. It literally means vertical and cross wise operations. It eliminates unwanted multiplication and allows the parallel creation of partial products and addition steps. The adders are utilized to append the partial-product generated in the Vedic mathematics methodology to drops the combinational lag. MAC is an essential unit in the digital signal processors, to show the characters like speed, power as well as area. Hence, ner multiplier plans are to increase the order of the system. The Modi ed sum product algorithm based Vedic multiplier is one such promising solution. It has a rapid multiplication process and reaches a less calculation complexity above its traditional multiplier. Array multiplier, Baugh-Wooley multiplier, Wallace-tree multiplier and Vedic multiplier were created in the existing work. In proposed work Vedic multiplier, using modi ed sum product algorithm was designed. The structure design coded in verilog and parameter analysis was done in Xilinx. The parameters like delay as well as power were compare between existing and proposed. When comparing with different multiplier with our proposed work delay get reduced. Comparing with existing multiplier the proposed 4x4 Vedic multiplier have 49.12% reduction in delay. Comparing with existing multiplier the proposed Vedic 4x4 multiplier have 42.51% reduction in power.

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Novel architecture of four quadrant analog multiplier/divider circuit employing single CFOA

Raj

Bhaskar

Kumar

2021

Analog Integr Circ Sig Process

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New current‐mode RMS‐to‐DC converters and four‐quadrant multiplier/divider based on VDTA

Cited by 8 publications

References 46 publications

New full‐wave rectifier based on modified voltage differencing transconductance amplifier

New full‐wave rectifier based on modified voltage differencing transconductance amplifier

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

Novel architecture of four quadrant analog multiplier/divider circuit employing single CFOA

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