New Design of RNS Subtractor for modulo 2>sup<n>/sup<+ 1

On the Design of Modulo 2 n ±1 Subtractors and Adders/Subtractors

“…Comparing the subtractors of [31] with the proposed ones, we can notice that the 2-input binary adder of [31] and the IEAC adder have similar area and delay requirements. The architecture of [31] further requires a 3-input binary adder and a (n + 1)-bit 2-to-1 multiplexer, whereas the proposed architecture, besides the IEAC adder, requires an IEAC CSA which mainly consists of half adders, and n 2-input logic gates.…”

“…We compare our proposal against the recently proposed subtractors for the normal representation [31]. The architecture of [31] was based on the following equation:…”

“…To implement (5), [31] first converts the input operands A and B from unsigned numbers to the signed ones. It then computes both terms of (5) in parallel, using one 2-input binary adder and one 3-input binary adder.…”

“…The architecture of [31] further requires a 3-input binary adder and a (n + 1)-bit 2-to-1 multiplexer, whereas the proposed architecture, besides the IEAC adder, requires an IEAC CSA which mainly consists of half adders, and n 2-input logic gates. Hence, we expect that the proposed subtractors will result in significantly less area and delay than those of [31].…”

“…Examples in digital signal processing (DSP) include linear-phase FIR filters with antisymmetric impulse responses, such as digital Hilbert transformers and differentiators, reduced-complexity complementary and parallel FIR structures, and adaptive DSP algorithms, such as channel equalizers and echo cancellers [27,38]. However, little work has been presented on the design of modulo 2 n ± 1 subtractors [5,31,32].…”