New interconnect plasma induced damage analyzed by flash memory cell array

Takebuchi, M.; Yamada, K.; Nishimura, Tadashi; Isobe, K.; Uemura, Tomomasa; Fujimoto, T.; Arakawa, Masashi; Mori, S.; Kimitsuka, A.; Yoshikawa, K.

doi:10.1109/iedm.1996.553150

Cited by 8 publications

(4 citation statements)

References 1 publication

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“…Finally, we should note that the suggested positive charge buildup is not due to backend plasma process such as VIAetching [4], since both cells with and without n -gated protection diode still exhibit fast-erasing phenomena in split-A. These results further support that the plasma damage to tunnel oxide is caused by the FG etching itself, prior to the formation of metal interconnection lines and VIA-holes.…”

Section: Discussionsupporting

confidence: 51%

“…A number of studies have shown that such an over-erase could be caused by clusters of positive charges in the tunnel oxide [1], potential fluctuation at poly-Si SiO interface due to a variation of poly-Si grain size [2], [3]. Also, much attention has been paid to the in-line processes, such as contact and via etch, which could degrade tunnel oxide quality and alter the erase characteristics owing to the plasma process-induced damage [4], [5]. However, little has been known regarding the relationship between the plasma damage during floating gate (FG) dry etching and erase characteristics in flash memory fabrication.…”

Section: Introductionmentioning

confidence: 98%

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Impact of floating gate dry etching on erase characteristics in NOR flash memory

Lee

et al. 2002

IEEE Electron Device Lett.

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We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate FowlerNordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si SiO 2 interface during the FG dry-etching, prior to the backend processes such as metal-or via-etch. Index Terms-Flash memory, Fowler-Nordheim (FN) tunneling, over-erase, plasma damage.

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Section: Discussionsupporting

confidence: 51%

Section: Introductionmentioning

confidence: 98%

Impact of floating gate dry etching on erase characteristics in NOR flash memory

Lee

et al. 2002

IEEE Electron Device Lett.

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“…14) Afterwards, PID has been regarded as critical issues in the fabrication of MOSFETs. In addition, PID to other devices such as memory, 21,22) image sensor, 23,24) power device, 25,26) and optical device 27,28) has been studied over the last four decades, where the degradation of these device parameters was investigated. PID is thus regarded as one of the principal issues in the development of not only leading-edge Si-based devices but also other functional devices in a wide variety of applications.…”

Section: Introductionmentioning

confidence: 99%

Characterization techniques of ion bombardment damage on electronic devices during plasma processing—plasma process-induced damage

Eriguchi

2021

Jpn. J. Appl. Phys.

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Plasma processing plays an important role in manufacturing leading-edge electronic devices such as ULSI circuits. Reactive ion etching achieves fine patterns with anisotropic features in metal-oxide-semiconductor field-effect transistors (MOSFETs). In contrast, it has been pointed out over the last four decades that plasma processes not only modify the surface morphology of materials but also degrade the performance and reliability of MOSFETs as a result of defect generation in materials such as crystalline Si substrate and dielectric films. This negative aspect of plasma processing is defined as plasma (process)-induced damage (PID) which is categorized mainly into three mechanisms, i.e. physical, electrical, and photon-irradiation interactions. This article briefly discusses the modeling of PID and provides historical overviews of the characterization techniques of PID, in particular, by the physical interactions, i.e. ion bombardment damage.

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“…In modern process technologies, PID is believed to significantly impact the performance of MOSFETs and other devices such as memory, 48,49) image sensor, 50,51) power device, 52,53) and optical device. 54) Approaches for suppressing PID in the field of plasma design should be carried out in combination with device and circuit designs, since higher performance is required with low ULSI chip cost and a rapid time-to-market.…”

Section: Introductionmentioning

confidence: 99%

Defect generation in electronic devices under plasma exposure: Plasma-induced damage

Eriguchi

2017

Jpn. J. Appl. Phys.

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The increasing demand for higher performance of ULSI circuits requires aggressive shrinkage of device feature sizes in accordance with Moore's law. Plasma processing plays an important role in achieving fine patterns with anisotropic features in metal-oxide-semiconductor field-effect transistors (MOSFETs). This article comprehensively addresses the negative aspect of plasma processingplasma-induced damage (PID). PID naturally not only modifies the surface morphology of materials but also degrades the performance and reliability of MOSFETs as a result of defect generation in the materials. Three key mechanisms of PID, i.e., physical, electrical, and photon-irradiation interactions, are overviewed in terms of modeling, characterization techniques, and experimental evidence reported so far. In addition, some of the emerging topicscontrol of parameter variability in ULSI circuits caused by PID and recovery of PIDare discussed as future perspectives.

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New interconnect plasma induced damage analyzed by flash memory cell array

Cited by 8 publications

References 1 publication

Impact of floating gate dry etching on erase characteristics in NOR flash memory

Impact of floating gate dry etching on erase characteristics in NOR flash memory

Characterization techniques of ion bombardment damage on electronic devices during plasma processing—plasma process-induced damage

Defect generation in electronic devices under plasma exposure: Plasma-induced damage

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