New layout generator for analog CMOS circuits

Yılmaz, Emre; Dündar, Günhan

doi:10.1109/ecctd.2007.4529530

Cited by 7 publications

(2 citation statements)

References 10 publications

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“…The minimum-Steiner-tree method used for net-length estimation considers the net sensitivity and channel congestion. A channel-inspired detailed router is also employed in ALG (2007-09) [110] [111]. Quite recently, and as a final note, Wei and Murmann (2021) discussed the application of digital place-and-route tools to the design of analog and mixed-signal blocks on a 16-nm FinFET CMOS technology [112].…”

Section: A Preliminaries: Digitally-inspired Strategiesmentioning

confidence: 99%

Analog Integrated Circuit Routing Techniques: An Extensive Review

Martins

Lourenço

2023

IEEE Access

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Section: A Preliminaries: Digitally-inspired Strategiesmentioning

confidence: 99%

Analog Integrated Circuit Routing Techniques: An Extensive Review

Martins

Lourenço

2023

IEEE Access

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“…This methodology intends to provide SPICE netlists with appropriately sized devices, but does not deal with any layout related issues. For automation of analog circuit layout refer to ALG [3] and LAYGEN [4].…”

Section: A Analog Circuit Design Automationmentioning

confidence: 99%

Automated G<inf>m</inf>C filter design: A case study in accelerated reuse of analog circuit design

Modi

Askari

Manohar

et al. 2010

2010 IEEE Dallas Circuits and Systems Workshop

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The increasing complexity of analog design for SoCs has become a bottleneck due to the lack of established design automation flows. Consequently, reuse of analog design IP (intellectual property) is becoming increasingly prevalent in the semiconductor industry. Traditional design reuse approaches still require a considerable amount of a designer's time for a new set of specifications or migration to new technology nodes. This paper describes an accelerated design reuse strategy for analog circuit design using design automation techniques. As a case study, we developed an automated G m C filter design flow using a combination of heuristic and stochastic optimization methods. The resultant IP is capable of generating SPICE netlists for wide sets of specifications and different technology nodes with minimal designer effort.

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Analog Layout Synthesis

Graeb¹

2011

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New layout generator for analog CMOS circuits

Cited by 7 publications

References 10 publications

Analog Integrated Circuit Routing Techniques: An Extensive Review

Analog Integrated Circuit Routing Techniques: An Extensive Review

Automated G<inf>m</inf>C filter design: A case study in accelerated reuse of analog circuit design

Analog Layout Synthesis

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