New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic

Abstract

Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.

Bus Implementation Using New Low Power PFSCL Tristate Buffers

“…It is found that all the proposed topologies consume half the power compared to the available switch based PFSCL tristate buffer [11] due to the fact that they all possess the provision of disabling the current flow in the high impedance state. In terms of propagation delay, it can be observed that all the topologies have almost equal delays since all of these possess similar loads and maintain the same bias current in the enabled state.…”

“…An additional Enable signal is employed to achieve the desired functionality. In literature, two topologies to implement PFSCL tristate buffer are available [11]. These topologies use either a switch or a sleep transistor to attain a high impedance state.…”

“…The other PFSCL tristate buffer [11], drawn in Figure 1(b), uses a sleep transistor M6 in series to the power supply terminal of the basic PFSCL buffer. It acts as regular buffer for low value of Enable signal by turning ON transistor M6 while providing a high impedance state at the output, otherwise.…”

“…A typical bus system has many tristate buffers attached to a common node. The study of PFSCL tristate buffers/inverters reveals that only two topologies are available [11]. These topologies use either a switch or a sleep transistor to attain the tristate behavior.…”

“…These topologies use either a switch or a sleep transistor to attain the tristate behavior. The suitability of the sleep transistor and the switch transistor based PFSCL tristate buffers [11] in bus system implementation is investigated and the drawbacks are identified. New PFSCL tristate buffers for this purpose are presented in this work.…”