New multi-step UV curing process for porogen-based porous SiOC

Seo, K.; Oka, Yoshihiro; Nomura, K.; Tsutsue, M.; Kobori, Etsuyoshi; Goto, Kazuya; Mizukami, Yumiko; Ohtsuka, Toshihiro; Tsukamoto, Kazuyoshi; Matsumoto, Susumu; Ueda, Tetsuya

doi:10.1109/iitc.2009.5090352

Cited by 3 publications

(2 citation statements)

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“…However, changes in stress state can be induced in other films in the dielectric stack [ 50 ] and excessive curing can actually damage pSiCOH films [ 51 ]. Multistep processes have been proposed to optimize porogen removal and mechanical properties separately [ 52 ].…”

Section: Dielectric Deposition Processesmentioning

confidence: 99%

Porous Dielectrics in Microelectronic Wiring Applications

McGahay

2010

Materials

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Porous insulators are utilized in the wiring structure of microelectronic devices as a means of reducing, through low dielectric permittivity, power consumption and signal delay in integrated circuits. They are typically based on low density modifications of amorphous SiO2 known as SiCOH or carbon-doped oxides, in which free volume is created through the removal of labile organic phases. Porous dielectrics pose a number of technological challenges related to chemical and mechanical stability, particularly in regard to semiconductor processing methods. This review discusses porous dielectric film preparation techniques, key issues encountered, and mitigation strategies.

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Section: Dielectric Deposition Processesmentioning

confidence: 99%

Porous Dielectrics in Microelectronic Wiring Applications

McGahay

2010

Materials

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“…Thus, several kinds of lower k-value dielectric materials (k < 2.5) have been studied. [1][2][3][4][5][6][7][8][9][10][11][12] However, they have posed many critical issues in the integration such as the degradation of film properties due to the post-process damages [13][14][15] and the weak tolerance against chip packaging due to the fragility of dielectric films and the weak adhesion strength between lower k-value dielectric materials and the underlying liner layer. In addition, shrinking both the size of via and the misalignment margin has essentially become difficult due to the technical limit of the lithography process.…”

Section: High-performance Extremely Low-k Film Integration Technologymentioning

confidence: 99%

High-Performance Extremely Low-k Film Integration Technology with Metal Hard Mask Process for Cu Interconnects

Torazawa

Matsumoto

Harada

et al. 2016

ECS J. Solid State Sci. Technol.

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High performance copper interconnects using extremely low-k film for the interlayer dielectric with the metal hard mask process and the interfacial surface oxygen treatment between extremely low-k film and liner layer was demonstrated. To suppress the process damage of interlayer dielectric and enlarge the space between vias and lines with a wide margin of lithography process, the robust extremely low-k film with the metal hard mask self-aligned via process was developed. The ultimate low capacitance wiring was achieved with the metal hard mask process, and the high reliability performance of time dependent dielectric breakdown between Cu lines with vias was accomplished by controlling the etching selectivity of the metal hard mask and the interlayer dielectrics. The adhesion strength between extremely low-k film and silicon carbide based liner layer was enhanced by controlling the composition of oxygen and carbon at the interface, resulting in the strengthening of the tolerance against chip packaging and thus the highly reliable chip packaging. This metal hard mask self-aligned via process with extremely low-k film and the interfacial surface oxygen treatment was demonstrated to be high performance, and therefore it offers a promising technology for Cu interconnects. Becoming the wiring pitches smaller as well as reducing the kvalue of dielectric materials are continuously required to achieve the high performance copper (Cu) interconnects which have higher speed, lower power and higher density. Thus, several kinds of lower k-value dielectric materials (k < 2.5) have been studied.1-12 However, they have posed many critical issues in the integration such as the degradation of film properties due to the post-process damages [13][14][15] and the weak tolerance against chip packaging due to the fragility of dielectric films and the weak adhesion strength between lower k-value dielectric materials and the underlying liner layer. In addition, shrinking both the size of via and the misalignment margin has essentially become difficult due to the technical limit of the lithography process. Hence, the degradation of reliability performance such as time dependent dielectric breakdown (TDDB) lifetime between Cu lines with vias is one of the most critical issues. Therefore, the self-aligned via process has been reported, [16][17][18][19] and the metal hard mask (MHM) process has been studied 20-32 instead of the conventional resist mask process to suppress the damage of interlayer dielectrics by the ashing process with oxygen (O 2 ) plasma. [33][34][35] We have studied the MHM process using the low stress TiN mask which had a fiber-textured structure for the perfect Cu filling and it has been demonstrated to be high performance. 36 However, the reports on the integration of lower k-value dielectric materials (k < 2.5) with the MHM self-aligned via process have been limited, and the complete process including reliability performance in chip packaging has not been reported.In this paper, high performance Cu interconnects using...

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