New Parallel Prefix Algorithm for Multicomputers

Abstract

A new computation-efficient parallel prefix algorithm for message-passing multicomputers is presented. The algorithm uses only half-duplex communications. It provides the flexibility of choosing parameter values for either fewer computation time steps or fewer communication time steps to achieve the minimal running time based on the ratio of the time required by a communication step to the time required by a computation step. Thus, under certain conditions, the new algorithm can run faster than previous ones for the same multicomputer model.

Dynamic-width reconfigurable parallel prefix circuits

“…, x n , and for a binary associative operation *, the prefix computation of the sequence is defined as outputs y i , 1 ≤ i ≤ n, y i = x 1 * x 2 * · · · * x i . Numbers of parallel prefix combinational structures have been proposed over the past years [4][5][6][7][8][9][10][11][12][13][14][15]. These combinational circuits intend to optimize area and speed through having circuits of minimum depth and/or size [16,17] (the depth of a circuit is the number of levels in the circuit, while the size is the number of operation nodes in the circuit).…”