New Radix-2 to the 4th Power Pipeline FFT Processor

4k-point FFT algorithms based on optimized twiddle factor multiplication for FPGAs

“…The lower resolution N ≤ 16, complex multiplier can be implemented with dedicated constant multiplier [5], [8]. .…”

Twiddle factor memory switching activity analysis of radix-2² and equivalent FFT algorithms

“…In this algorithm, the 256-point DFT is decomposed based on the radix-2 2 [3] for the first stages, then the modified radix-2 4 [5] in applied to the remaining stages. The radix-(2 2 &M.2 4 ) algorithm is characterized that it has same twiddle factor complex multiplier as the radix-2 2 for the W N multiplier.…”

“…Especially, one can note that for a W 4 multiplier the possible coefficients are {±1, ±j} and, hence, this can be simply solved by optionally interchanging real and imaginary parts and possibly negate (or replace the addition with a subtraction in the subsequent stage). In [5], [8] twiddle factor multiplier for {W 8 , W 16 , and W 32 } using constant multiplication were proposed. However, a common way to solve the twiddle factor multiplication is to use a general complex mulitplier and precompute the twiddle factors and store in a memory.…”

Memory efficient DIT-based SDF IFFT for OFDM systems

“…For the implementation of IFFT/FFT, the pipelined architectures are widely used since they offer high throughput and low latency, as well as a reasonable low area and power consumption. Among the various pipelined IFFT/FFT architectures, the single-path feedback (SDF) approach based on the radix-2 r algorithm is frequently used for its low cost and high efficiency [1,2,3].…”