New Resistor-Less Electronically Controllable ±C Simulator Employing VCII, DVCC, and a Grounded Capacitor

Abstract

In this paper, a new realization of electronically controllable positive and negative floating capacitor multiplier (±C) is presented. The peculiarity of the presented topology is that, for the first time, it implements a floating equivalent capacitor between its two input terminals, rather than a grounded one. To achieve the best performance, we simultaneously use the advantages provided by the current conveyor and its dual circuit, the voltage conveyor. The proposed topology is resistor free and employs one dual-output second-generation voltage conveyor (VCII±) and one electronically tunable differential voltage current conveyor (E-DVCC) as active building blocks (ABBs) and a single grounded capacitor. The value of the simulated capacitor is controlled by means of a control voltage VC which is used to control the current gain between X and Z terminals of E-DVCC. The circuit is free from any matching condition. A complete non-ideal analysis by considering parasitic impedances as well as non-ideal current and voltage gains of the used ABBs is presented. The proposed circuit is designed at the transistor level in 0.18 µm and ±0.9 V supply voltage. Simulation results using the SPICE program show a multiplication factor ranging from ±10 to ±25.4 with a maximum error of 0.56%. As an example, the application of the achieved floating capacitor as a standard high pass filter is also included.

New negative‐grounded capacitance multiplier circuits

“…Since, in this paper, we have proposed new configurations of negative capacitance multiplier; therefore, a brief summary of previously reported negative capacitance multipliers employing different ABBs along with CFOAs [25][26][27][28][29][30][31][32][33][34][35][36][37] has been presented here to put the proposed work in proper perspective.…”

“…1. Use of more than one ABB 25,26,[28][29][30][31][32][34][35][36][37] 2. Employment of floating capacitor 25,[27][28][29]31,32,[34][35][36][37] 3.…”

“…Employment of floating capacitor 25,[27][28][29]31,32,[34][35][36][37] 3. Use of nonavailable off-the-shelf IC [26][27][28][29][30][31] 4. Requirement of matching constraint 31,33 5.…”

“…Requirement of matching constraint 31,33 5. Low MF (<200) [27][28][29][30][31][32] In view of the above, it appears that no single CFOA-based negative capacitance multiplier has been presented yet, which can provide high MF (>1200), employing grounded capacitor without any passive component matching condition(s). Therefore, the main aim of this communication is to present new negative capacitance multiplier circuits with features not available in existing NGCM circuits as shown in Table 1.…”

“…For low frequency applications, mostly higher value capacitance is used that increases the size of capacitor (which requires large area on silicon chip and not suitable from the view point of IC fabrication) 1–3 . Consequently, to alleviate these limitations, researchers and circuit designers have stimulated various positive CMs 4–24 and negative CMs, 25–37 employing different active building blocks. These CMs may find various applications in the design of low frequency filters, low frequency oscillators, and integration of a phase‐locked loop filter 38 .…”