New structures of the concurrent error detection systems for logic circuits

Sapozhnikov, Vladimir; Ефанов, Д.В.; Дмитриев, В. В.

doi:10.1134/s0005117917020096

Cited by 26 publications

(13 citation statements)

References 14 publications

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“…In [19], a standard structure is described, organized using a transitions weight-based sum code between bits occupying adjacent positions in data vectors. It possesses "good" detecting properties, however, it has a high structural redundancy of the final device.…”

Section: Abstract: Self-checking Built-in Control Circuit Checking Of...mentioning

confidence: 99%

Transitions weight-based sum code for the digital computing devices synthesis

Ефанов¹

2021

Èlektron. model.

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A method for constructing a family of sum codes is described based on weighting the transitions between groups of bits in the data vector. In this case, weights are used that are powers of the number 2. This makes it possible to obtain a code with check bits described by linear functions. The proposed weight-based sum code makes it possible to synthesize self-checking devices based on the standard elements and optimization methods of the logical device’s structures. A standard structure of a device with a concurrent error-detection (CED) circuit based on transitions weight-based sum codes between bits groups in the data vector is presented. The standard structure advantage lies in the possibility of synthesizing CED circuits with technical implementation reduced complexity by using codes with check bits numbers that are much smaller than the data bits numbers. Self-checking devices synthesized using the described codes in some cases may turn out to be less redundant than when using the standard duplication structure. The structure disadvantage is the need to consider the restrictions on the multiplicity of errors arising at the outputs of the diagnostic objects. This limitation increases with a decrease in the number of check bits. Despite this, in many cases, the use of a standard structure based on transitions weight-based sum code between groups of digits in the data vector makes it possible to synthesize self-checking digital devices. Using a standard structure for organizing a CED circuit allows going to implement of fault-tolerant digital devices according to standard structures, one of which is given in this article.

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Section: Abstract: Self-checking Built-in Control Circuit Checking Of...mentioning

confidence: 99%

Transitions weight-based sum code for the digital computing devices synthesis

Ефанов¹

2021

Èlektron. model.

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“…The proposed fault-tolerant structure is advisable to use for combinational automation devices. It is based on duplication with weighted-transitions sum code [12] control and makes it possible to synthesize fault-tolerant devices with less hardware redundancy compared to the structure of majority error correction by hardware redundancy.…”

Section: обчислювальні процеси та системиmentioning

confidence: 99%

“…This means that it is constructed using typical blocks, elements, converters, and standard structure optimization tools (for example, the P (x) block in Fig. 2) [12]. This feature provides these structures with a fairly wide application.…”

Section: обчислювальні процеси та системиmentioning

confidence: 99%

“…To improve error detection characteristics in checked devices, it is possible to use codes with a large number of detected errors. One of such codes is a code with summation of the weight coefficients of transitions between bits occupying adjacent positions in data vectors (a code with summation of weighted transitions), described in [12].…”

Section: обчислювальні процеси та системиmentioning

confidence: 99%

“…If the expression on the left side of (3) is equal to zero for all such elements, then there is no input set on which errors are transmitted to all outputs of the device. As indicated in [12], such properties of the T (m, k)-code make it possible to construct a typical structure of the self-checking integrated control circuit called the "almost duplication" structure that can be used as an alternative to the duplication system.…”

Section: обчислювальні процеси та системиmentioning

confidence: 99%

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Typical Structure of a Duplicate Error Correction Scheme with Code Control with Summation of Weighted Transitions

Ефанов¹,

Sapozhnikov²

2020

Èlektron. model.

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Error correction circuit typical structures are described-majority and duplication structure with control by parity. A new structure of the correction circuit based on duplication with weighted-transitions sum code control is proposed. The code is constructed by weighting the transitions between the adjacent bits in data vectors, numbers from sequentially increasing powers of the number «two», starting from the zero degree. The specified code detects any errors in data vectors, except for errors associated with distortions of all data bits at the same time. The weighted sum code features allow it to be used in the synthesis of error detection circuits. An example of the correction circuit synthesis is given. The experiments results using control combinational circuits MCNC Benchmarks showed that the duplication structure with weighted-transitions sum code control in many cases allows one to obtain lower complexity indicators values of the correction circuits technical implementation than the known structure of majority correction.

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Block diagram of the automatic model of technical documentation

Baratov¹,

Aripov²,

Muxiddinov³

et al. 2020

J. Phys.: Conf. Ser.

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The article explores the features of electronic document management of technical documentation of railway automation and telemechanics. The article deals with the synthesis of mathematical models of electronic document management of technical documentation of railway automation and telemechanics. For this purpose, the real processes of creation, verification and use of technical documentation were examined using the example of the process of accounting and control of railway automation and telemechanics devices, which made it possible to identify a structural diagram of a formalized model of technical documentation. A model of electronic document management of technical documentation is created using the mathematical apparatus of finite state machines. A block diagram of an automaton model of technical documentation is developed. The proposed block diagram of a formalized model of technical documentation consists of matrices of external microoperations, internal microoperations, code creation for the following microcomponents. The number of internal states of the firmware is completely determined by the number of logic elements of the algorithms. The size of the matrices depends on the number of operators and logical conditions in the logic circuits of the algorithms.

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New structures of the concurrent error detection systems for logic circuits

Cited by 26 publications

References 14 publications

Transitions weight-based sum code for the digital computing devices synthesis

Transitions weight-based sum code for the digital computing devices synthesis

Typical Structure of a Duplicate Error Correction Scheme with Code Control with Summation of Weighted Transitions

Block diagram of the automatic model of technical documentation

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