New test methodology for resistive open defect detection in memory address decoders

Azimane, Mohamed; Majhi, A.K.

doi:10.1109/vtest.2004.1299235

Cited by 21 publications

(8 citation statements)

References 15 publications

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“…In the presence of opens in such circuits, the whole writing path will be impacted and therefore such defects can be detected during the test of address decoder (delay) faults [3], [4], [5], [6], [7]. For this reason, this paper will deal only with shorts and bridges.…”

Section: Bit/byte Write Enable Defects/fault Modelsmentioning

confidence: 99%

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BIST enhancement for detecting bit/byte write enable faults in SOC SRAMs

Hamdioui

Al-Ars

Jiménez³

et al. 2008

2008 2nd International Conference on Signals, Circuits and Systems

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The continued increase of the integration density of systems on chip (SoCs) and the number of embedded memory blocks in them, together with the continued technology scaling, increases their sensitivity to a variety of potential manufacturing (new) defects. Standard march tests are usually used to achieve a good fault/defect coverage. This paper presents an experiment in diagnosing defects in the circuitry responsible for the realization of bit, byte or group write enable in memories. First defects in such circuitry are analyzed, and fault models together with an appropriate test algorithm are presented. Subsequently, the test is added to an existing BIST engine to target the bit/byte write enable faults. The preliminary silicon results of two experiments are presented. They validate some of the targeted fault models and show the importance of considering bit/byte write enable faults for high outgoing product quality.

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Section: Bit/byte Write Enable Defects/fault Modelsmentioning

confidence: 99%

“…They cause mainly time-related faults referred to as dynamic faults. Dynamic faults are divided into three types: (a) Dynamic Memory Cell Array Faults [6], [19], [20] (b) Dynamic/Delay Address Decoder Faults [3], [4], [5], [7] and (c) Dynamic Peripheral Circuit Faults [21], [22].…”

Section: Dynamic Testsmentioning

confidence: 99%

BIST enhancement for detecting bit/byte write enable faults in SOC SRAMs

Hamdioui

Al-Ars

Jiménez³

et al. 2008

2008 2nd International Conference on Signals, Circuits and Systems

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“…The work in [1] shows that the causes of image artifacts are strongly linked to the defects on pixel bias and addressing. A similar cause of failure has also been studied for memory circuits [2].…”

Section: Introductionmentioning

confidence: 99%

BIST of interconnection lines in the pixel matrix of CMOS imagers

Fei

Moreau

Mir

2013

5th IEEE International Workshop on Advances in Sensors and Interfaces IWASI

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ISBN : 978-1-4799-0039-8International audienceInterconnection lines in the sensors of CMOS imagers are used for pixel bias, addressing and readout. Catastrophic faults in these lines can cause parts of the pixel matrix to operate incorrectly and produce image defects like residual stripes and bands in images. These kinds of image defects are often difficult to remove by the image processing correction algorithm, and they are clearly visible as a sort of noise pattern. Among the defects in the pixel array, these catastrophic faults have most important influence on yield. In addition, partially degraded metal lines cannot be detected on todays' standard industrial testers for image sensors. These defects can evolve into catastrophic faults and they are the main cause of customer returns for many products. This paper proposes two built-in self-test (BIST) solutions to catch these defects in the pixel array, taking into account the industrial test constraints, namely increase of fault coverage, decrease of test time and test cost minimization

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“…O PEN defects are responsible for a high percentage of failures in interconnect lines and, as a consequence, are becoming a frequent defect type affecting present complementary metal-oxide-semiconductor (CMOS) integrated circuits [1]- [5]. A break may occur during some of the manufacturing process steps, causing a discontinuity at any physical line otherwise designed to electrically connect the two endpoints (nodes) of the line.…”

Section: Introductionmentioning

confidence: 99%