New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA

Abstract

Currently, reconfigurable hardware devices feature a high density of heterogeneous resources to enable multitasking and offer flexibility in application needs. These concepts raise the need for efficient management of hardware tasks and hardware resources. The scheduling of hardware tasks is highly dependent on placement. Placement focuses on allocation of hardware resources required by the scheduled hardware tasks. In this paper, we propose novel three-level resource management that investigates enhancement of placement quality by reducing task rejection, configuration overheads, and by optimizing resource utilization. Improving placement quality will produce significant enhancement of performance for scheduling and overall execution time of the application in FPGA. Hence, the placement problem is formulated into a constrained optimization problem and resolved with powerful solvers using the Branch and Bound method. The obtained results of an application of heterogeneous hardware tasks show an average resource utilization of 36% of the available resources on the reconfigurable region and an overall overhead of 11% of total application running time, and we have eliminated the issue of task rejection. Compared to static implementation, the gain in resource utilization within the reconfigurable region achieves up to 43%.

FoRTReSS: a flow for design space exploration of partially reconfigurable systems

“…Software context switches are processor dependent whereas for hardware implementations, this context switch depends on the implementation (two implementations of the same task might have different context switch times due to a different number of registers to save/restore, possibly some memories). Some work has been done on context switch for hardware tasks such as [5,17,20]. However, context switching is not required after a task configuration, but might be necessary for proper task execution (for instance, IP configuration).…”

FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA

“…integrating a DMA (Direct Memory Access) to increase the throughput of the configuration interface [5]. Scheduling may also be able to predict the tasks to execute on a reconfigurable zone (RZ) [6], thus bitstream pre-loading could significantly improve performance.…”