New Topology for Asymmetrical Multilevel Inverter: An Effort to Reduced Device Count

Abstract

Nowadays, multilevel inverters (MLI) are receiving remarkable attention due to salient features like less voltage stress on switches and low total harmonic distortion (THD) in output voltage. However, the required switch count increases with number of voltage levels. This paper presents a new topology for asymmetric multilevel inverter as a fundamental block. Each block generates 13-level output voltage using eight switches and four unequal dc voltage sources. The proposed configuration offers special features such as reduced number of switches, isolated dc sources, cost economy, less complex and modular structure than other similar contemporary topologies. Moreover, significant reduction in voltage stress on the circuit switches can be achieved. Comparative studies of proposed topology with the conventional and recent topologies have been presented in terms of power switches, gate driver circuit requirement, isolated dc voltage sources and total standing voltage. Multicarrier-based sinusoidal pulse width modulation (SPWM) scheme is adopted for generating switching signals using dSPACE real-time controller. In addition, proposed topology offers a fewer number of ON-state switches that lead to reduction in power loss. The proposed topology is validated through simulation and experimental implementation.

Modified “K”‐type multilevel inverter topology with reduced switches, DC sources, and power loss

“…This comparison illustrates the performance of the proposed topology and some existing topologies in asymmetrical source condition. Several algorithms are presented for the different numbers of voltage level generation in the considered topologies among them, the best one is considered for this comparison. Furthermore, the proposed topology and conventional topologies are analyzed with trinary source values.…”

“…The proposed structure is developed with reduced number of switches but the blocking voltage on the full bridge switches are high. The asymmetric topology with reduced power components is proposed . This topology uses two different dc source values for four dc sources.…”

A modified circuit for symmetric and asymmetric multilevel inverter with reduced components count

“…Thus, total power loss (P T ) using (13)- (17) can be written as P T ¼ P c;S þ P c;BD þ P swi;on þ P swi;off : Also t on and t off are on-state and off-state time of the switches.…”

“…[14][15][16][17][18][19] But, the main disadvantage of these topologies is high dv/dt stress on switches because of H-bridge at output terminals, which limits these topologies for high voltage applications. [14][15][16][17][18][19] But, the main disadvantage of these topologies is high dv/dt stress on switches because of H-bridge at output terminals, which limits these topologies for high voltage applications.…”

“…To overcome the shortcomings of the above addressed MLI topologies, several topologies with basic units have been proposed in the literature. [14][15][16][17][18][19] But, the main disadvantage of these topologies is high dv/dt stress on switches because of H-bridge at output terminals, which limits these topologies for high voltage applications. Many researchers have been working towards the new configurations for MLIs that requires lower number of devices, dc supplies, and reduced dv/dt stress on switches, [20][21][22][23][24][25][26][27][28][29][30] which are suitable for medium voltage applications.…”