1987 International Electron Devices Meeting 1987
DOI: 10.1109/iedm.1987.191485
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New ultra high density EPROM and flash EEPROM with NAND structure cell

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Cited by 156 publications
(49 citation statements)
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“…A completely different approach in array organization can be followed by using a NAND architecture, which greatly improves the results [82]. The elementary unit is not composed of the single three-terminal cell, which stores one single bit, but by more FG transistors connected in a series (eight or 16), which constitutes a chain connected to the bit line and ground through two selection transistors (Fig.…”
Section: H Nandmentioning
confidence: 99%
See 1 more Smart Citation
“…A completely different approach in array organization can be followed by using a NAND architecture, which greatly improves the results [82]. The elementary unit is not composed of the single three-terminal cell, which stores one single bit, but by more FG transistors connected in a series (eight or 16), which constitutes a chain connected to the bit line and ground through two selection transistors (Fig.…”
Section: H Nandmentioning
confidence: 99%
“…Fig. 41 shows the cross section of an 8-b elementary block for a 4-Mb Flash memory organized as a NAND array with peripheral circuits [82]. Erase voltages are 20 V to the n-substrate, the p-well2, the drain, and the source, and 0 V to the control gate of the selected location.…”
Section: H Nandmentioning
confidence: 99%
“…A FG has been the common approach for 2D NAND for over 20 years [6], offering reliable operation and, despite the complex structure, has still been manufactured down to below 16 nm. CT cells have already been proposed as a suitable candidate to replace FGs below 40 nm but finally have not been used in 2D NAND [7][8][9][10][11][12].…”
Section: The Storage Method: Transitioning From Floating Gate To Charmentioning
confidence: 99%
“…In the realm of non-volatile memories, SILC can lead to charge loss/gain from/to the floating gate after stress and to retention errors. To keep this contribution negligible, the oxide thickness of Flash cells has barely scaled with the technology generations, going from about 10 nm in the first prototype [3] to about 7-8 nm in the latest nodes [182]. However, experimental data [183][184][185][186][187][188] have demonstrated that, even if the SILC is reduced, there is a small number of cells that can exhibit a high leakage after stress, in analogy with the statistical behavior of RTN.…”
Section: Retention After Cycling and Silcmentioning
confidence: 99%
“…However, it was not until the development of the one-transistor Flash memory device [2], in which the entire chip could be erased at once, that solid-state non-volatile code and data storage began to experience a tremendous growth. Data storage, in particular, was fostered by the invention of the NAND Flash [3], which is possibly one of the most successful semiconductor devices ever developed. Thanks to its extremely compact area occupation and to clever system design and optimization, it benefited from the market explosion of digital cameras first, followed by smartphones and tablets and culminating in the development of NAND solid-state drives (SSDs) [4], that have recently overtaken hard-disk drives (HDDs) in terms of areal storage density [5].…”
Section: Introductionmentioning
confidence: 99%