Next Generation Panel-Scale RDL with Ultra Small Photo Vias and Ultra-Fine Embedded Trenches for Low Cost 2.5D Interposers and High Density Fan-Out WLPs

Liu, Fuhan; Kubo, Atsushi; Nair, Chandrasekharan; Ando, Tomoyuki; Furuya, Ryuta; Dwarakanath, Shreya; Tummala, Rao

doi:10.1109/ectc.2016.313

Cited by 12 publications

(5 citation statements)

References 7 publications

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“…On the other hand, this process is still semi-additive process (SAP) where Cu seed layer is initiated and etched afterward. Thus, the associated challenges with Cu seed based SAP process are still to be faced [9].…”

Section: Trends For Microvia Technology and Related Workmentioning

confidence: 99%

“…Advanced fan-out WLP requires interconnects in the range of 1 µm wide. With the current material technology and semi-additive process (SAP), this feature-size is not feasible due to the following [9]: 1) Surface roughness for better Cu seed adhesion limits this range of feature size. 2) Etching process causes deteriorate the shape of the interconnects.…”

Section: Semi-additive Process Challenges With Small Feature Sizementioning

confidence: 99%

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A novel production process for 10 μm microvias.

Renbi

Delsing

2017

International Symposium on Microelectronics

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This work investigates the capability of drilling and metallization of microvias of diameter less than 10 μm with aspect ratios of 1–10, using a fully additive process. The microvia has been produced using a sequential build up layer of urethane through which the via has been produced. The urethane layer is applied using spin-coating. Current process setting produces a 15 μm layer thickness. For thicker urethane, multiple layers are applied. Drilling of the via-hole through is made using 266 nm UV laser. The metallisation of the via-hole was made using a process called Covalent Bonded Metallisation (CBM). This process modifies the urethane surface by a grafting process where polymers are covalently bonded to the surface where metallisation is desired. A roughly 5 μm thin film of the used grafting solution is applied to the substrate surface. The grafting process is initiated by laser which draws the patterns where copper is desired. After laser drawing, the substrate is cleaned with deionized water. Next, the substrate is through a commercial chemical-copper process which builds copper only at the laser initiated patterns. Copper thicknesses of 1 μm is easily achievable. To increase the copper thickness, the substrate may be run into thick building chemical-copper process to achieve thicknesses up to 8 μm.

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Section: Trends For Microvia Technology and Related Workmentioning

confidence: 99%

Section: Semi-additive Process Challenges With Small Feature Sizementioning

confidence: 99%

A novel production process for 10 μm microvias.

Renbi

Delsing

2017

International Symposium on Microelectronics

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“…Even though previous studies show an improvement in the die shift issue during the process, the total shift value was still in the range of 30–45 μm and a subsequent RDL process was required for a more accurate position of the die to interconnect the die pad with an RDL via. Moreover, the scalability of the RDL is getting finer and the RDLs are approaching a 2/2 μm line width and line spacing [7]. Therefore, minimising the die shift value is very important for the advanced device packaging by FOWLP technology.…”

Section: Introductionmentioning

confidence: 99%

Process enabling highly accurate die position for fan‐out package applications

Park¹,

Kim²

2017

Electron. lett.

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A new process that can improve die shift issue in process utilising back-sided under bump metallurgy (UBM) via a self-alignment effect for fan-out package applications is proposed. The die and the pad of the substrate are spontaneously aligned and the degree of accuracy is very high after reflow. For the experiment, two kinds of UBM pads were prepared on glass dies and the SAC305 solder was formed on the copper pads of an frame retardent (FR)-based substrate. The die shift value was from 20 to 50 μm after pick-and-placement. After reflow, the maximum die shift value was <1 μm. An initially misaligned die with a large shift was aligned with a high degree of accuracy during reflow due to the surface tension of the molten solder. The proposed process improves the die shift issue in the fabrication of fan-out wafer-level packaging and the active die embedded substrate.

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“…Recently, the RDL was shrunken to fine pitch line/space (below 1.5 μm/1.5 μm) to increase the device density for high performance. 6,7 However, because of the anisotropic and poorly controlled etching of fine pitch lines, the SAP suffers from limitations such as undercutting, collapse, over-etching, and delamination during the Cu seed layer etching, 6,8 thereby decreasing the reliability of the package devices. Thus, the damascene process for RDL has been introduced to overcome these etching problems.…”

mentioning

confidence: 99%

“…Thus, the damascene process for RDL has been introduced to overcome these etching problems. 7,9 The damascene process for the RDL is performed according to the following steps: PR patterning, barrier/seed layer deposition, and Cu electrodeposition. However, overburden formation on the pattern is inevitable during Cu electrodeposition and requires a surface planarization process to remove these overburdens for the subsequent RDL layers.…”

mentioning

confidence: 99%

Selective Copper Electrodeposition for Redistribution Layer by Varying Concentration and Agitation of Janus Green B

Lee,

Kim,

Han

et al. 2023

ECS J. Solid State Sci. Technol.

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A fine-pitch redistribution layer (RDL) for high-performance devices in a fan-out wafer-level package (FOWLP) is required in semiconductor packaging technology. The damascene process for fine-pitch RDL has been studied for several years, which has been introduced to overcome the etching problems. Although surface planarization for removing overburden is necessary for the damascene process in RDL, it adds high cost to the FOWLP process. Selective Cu electrodeposition is a method used to prevent overburden. Janus Green B (JGB) is utilized as a leveler in Cu electrodeposition and has properties that depend on concentration and agitation. These properties affected the Cu deposition rate according to the pattern position. Thus, the electrochemical properties of JGB were investigated based on the concentration of JGB and agitation. Furthermore, the effect of JGB on the crystalline structure of the Cu film was examined. Additionally, changes in the growth behavior of the Cu nuclei caused by JGB were observed during the initial stage of chronoamperometry. Based on these results, selective Cu electrodeposition was successfully performed on the patterned substrate using the difference in the concentration of JGB and agitation.

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Next Generation Panel-Scale RDL with Ultra Small Photo Vias and Ultra-Fine Embedded Trenches for Low Cost 2.5D Interposers and High Density Fan-Out WLPs

Cited by 12 publications

References 7 publications

A novel production process for 10 μm microvias.

A novel production process for 10 μm microvias.

Process enabling highly accurate die position for fan‐out package applications

Selective Copper Electrodeposition for Redistribution Layer by Varying Concentration and Agitation of Janus Green B

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