Ni/Ag metallization for SiGe HBTs using a Ni silicide contact

Abstract

We developed a self-aligned low-temperature process for the production of SiGe hetero bipolar transistors (HBTs) using a new metallization scheme with Ni/Ag taking advantage of the low specific resistivity of Ag and good contact resistance and low silicon consumption of the Ni silicide. Gummel plots of fabricated HBTs show sufficiently good behaviour. The formation of Ni silicide over temperature (325-500 • C) in a rapid thermal process system is studied. At temperatures above 425 • C a rather smooth film of monosilicide NiSi is formed. The resistivity of the thin (110 nm) NiSi was found to be excellent (11 µ cm) compared with bulk values. The contact resistance to n-and p-type silicon of 5 × 10 19 cm −3 is determined. Formation of self-aligned Ni silicide/Ag contacts is investigated and compared to non-self-aligned contacts.

Spontaneous Chemical Vapor Growth of NiSi Nanowires and Their Metallic Properties

“…The measured resistivity is higher than the lowest value of 10 lX cm of NiSi thin films and nanowires measured with four-probe configurations, which can preclude contact resistance. [3,15,16] At the moment the relatively higher resistivity of the NiSi nanowires reported here are currently under investigation. Nevertheless, as in Figure 3b, the measured resistivity linearly decreases with decreasing temperature down to 77 K, as is typically expected for a metal.…”

Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base

“…A self-aligned silicide, typically CoSi 2 , is also used to obtain low contact and sheet resistance [3]. NiSi integration in bipolar processes has previously been demonstrated for Si-devices [4] and SiGe HBTs [5]. In this study we demonstrate the integration of nickel silicide in a quasi self-aligned (QSA) SiGeC HBT structure for the first time to our knowledge.…”

Monolithic Integrated Coplanar W-Band Impatt Oscillator

“…The device formation ( Fig. 1) is based on a double mesa structure without planarization because of the relaxed lithography rules, low temperature processing is provided by dry etching of Si (nominal room temperature, actual < 200°C), passivation by plasma enhanced chemical vapor deposition (PECVD, 350°C) of oxid, sputter deposition of contact metals (Al, Ni) and annealing (450°C for NiSi contacts [2]). …”