Nickel vs. cobalt silicide integration for sub-50nm CMOS

Froment, B.; Müller, Markus; Brut, H.; Pantel, R.; Carron, V.; Achard, H.; Halimaoui, A.; Bœuf, F.; Wacquant, F.; Regnier, C.; Ceccarelli, Daniele; Palla, R.; Beverina, A.; DeJonghe, V.; Spinelli, P.; Leborgne, O.; Bard, K.; S, Sudha Maria Lis; Tirard, V.; Morin, Pascal; Trentesaux, F.; Gravey, V.; Mandrekar, T.; Rabilloud, D.; Van, S.; Olson, E.; Diedrick, J.

doi:10.1109/essderc.2003.1256852

Cited by 16 publications

(7 citation statements)

References 2 publications

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“…The 2.8 nm thick gate oxynitride insulator film and the poly-Si gate electrode layer were formed on a P type Si substrate. The cobalt (Co) silicide film was formed on the poly-Si electrode [8][9][10]. The poly-Si layer was deposited at 620 o C in the furnace as shown in Fig.…”

Section: Sample Preparationmentioning

confidence: 99%

On the Origin of the Gate Oxide Failure Evaluated by Raman Spectroscopy

Yokogawa

Tomita

Mizukoshi³

et al. 2015

ECS Trans.

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The metal-oxide-semiconductor-field-effect-transistor (MOSFET) has been miniaturized for the high performance large-scale integrated-circuit (LSI). However, in the ultimately miniaturized MOSFET, the gate oxide failure with high leakage current is inevitable. In this study, we evaluated the origin of the gate oxide failure by Raman spectroscopy in conjunction with optical beam induced resistance change (OBIRCH) analysis. MOS capacitors were used as the samples. The 2.8 nm thick gate oxinitrid insulator film and the poly-Si gate electrode layer were formed on a P type Si substrate. The cobalt (Co) silicide film was formed on the poly-Si electrode. The SiH4 flow rate was 150 sccm or 350 sccm. The gate oxide integrity was evaluated by the test element group (TEG) measurements. As a result, Raman intensity increased at the failure position compared with the other positions in the sample deposited with 150 sccm of SiH4 flow rate. We consider that higher Raman intensity at the gate oxide failure positions reflects the irregular structure of poly-Si. Furthermore, the Raman peaks at failure positions shifted toward the lower wavenumber while the FWHMs are approximately constant with other positions. Thus, we found that there is no difference in the crystallinity of the poly-Si. The origin of the gate oxide failure was high tensile strain in the gate poly-Si electrode. In conclusion, we have successfully evaluated the gate oxide failure by Raman spectroscopy with a quasi-line excitation source.

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Section: Sample Preparationmentioning

confidence: 99%

On the Origin of the Gate Oxide Failure Evaluated by Raman Spectroscopy

Yokogawa

Tomita

Mizukoshi³

et al. 2015

ECS Trans.

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“…NiSi has low reaction temperature, low resistivity, and lower silicon consumption than CoSi 2 . [ 15–18 ] In addition, NiSi does not exhibit a bridge effect or narrow linewidth effect at a small scale. Thus, NiSi was commonly applied to study the reduction in the contact resistance of planar devices until the appearance of FinFETs at the 14 nm technology node.…”

Section: Introductionmentioning

confidence: 99%

Design on Formation of Nickel Silicide by a Low‐Temperature Pulsed Laser Annealing Method to Reduce Contact Resistance for CMOS Inverter and 6T‐SRAM on a Wafer‐Scale Flexible Substrate

Hsu,

Chen,

Shieh

et al. 2023

Adv Elect Materials

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A pulsed laser annealing method is utilized to directly synthesize nickel silicide (NiSi) as a contact material to improve the contact of electric devices. Three laser wavelengths, 355 nm (ultraviolet laser), 532 nm (green laser), and 1064 nm (infrared laser), are used for the NiSi synthesis during the pulsed laser annealing process. A NiSi phase with low sheet resistance is formed by an ultraviolet laser annealing (ULA) process without damaging the polyimide (PI) substrate. With the integration of the ULA process‐induced NiSi into p‐nnel MOSFET (PMOS) and n‐channel MOSFET (NMOS) devices, the on/off ratio improves significantly, and the field‐effect mobility increases by 30% because of the reduction in contact resistance from 21 to 8.5 kΩ. In addition to the PMOS and NMOS, the gains of the CMOS inverter at different Vdd values are improved by at least 30%. Moreover, the static noise margin of 6T‐SRAM is elevated from 0.82 to 1 V at Vdd = 4 V. The ability of the ULA process to synthesize a high‐quality NiSi layer on a flexible substrate is demonstrated. The integration of NiSi into electrical devices offers a new pathway for improving the electrical behavior of flexible devices.

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“…In most studies, relatively thick silicide films are formed with an initial thickness of a deposited metal from 50 to 100 nm. For these thickness ranges, it has been shown that the phase formation sequence of nickel silicide for an increasing thermal budget is as follows [1,2]:…”

Section: Introductionmentioning

confidence: 99%

Effect of Vacuum Annealing Temperature on the Binary System Ni/Si(100)

Mezouar¹,

Merabet²,

Bahloul³

2020

J. Nano- Electron. Phys.

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Metal silicide films are widely applied in microelectronic industry, they have been used as rectifier and ohmic contacts. Most of metals react with silicon to form silicide, the deposition of a thin metal layer is obtained by different techniques. The common methods are vacuum evaporation with filament or e-gun, sputtering, and chemical vapor deposition. The vacuum deposition of a thin layer of metal on a silicon substrate is one of the most widely used. The metal silicide film is grown on a silicon substrate and then annealed at different thermal budgets. In this work, to prepare a silicide film, we have used as a technique vacuum evaporation PVD (physical vapor deposition) by using a nickel (Ni) filament with high purity. On a substrate of naturally oxidized Si(100) and after HF surface preparation, two layers of nickel are deposited, namely of 56 nm and 35 nm. These different samples (Ni(56 nm)/Si(100) and Ni(35 nm)/Si(100)) were then vacuum annealed at different thermal budgets and at temperatures equal to 350, 500, 650 and 750 °C for a time equal to 30 min. The characterization of the obtained layers was made by the following techniques: X-ray diffraction (XRD) for studying the structure of the films (phase identification), the four-point probe technique for measuring the sheet resistance of the phase(s), and the surface roughness study was carried out using atomic force microscopy (AFM). The growth of Ni on naturally oxidized Si(100) substrates has been studied by different techniques which confirmed that the vacuum annealing temperature has a very important effect, NiSi monosilicide phase appears from 650 °C. The morphology analysis of the interface revealed the presence of different phases NiSi, NiO and Ni2O3 which is confirmed by structural analysis. Also, good coherence was observed between XRD results with those of the sheet resistance and the RMS surface roughness measurements.

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Nickel vs. cobalt silicide integration for sub-50nm CMOS

Cited by 16 publications

References 2 publications

On the Origin of the Gate Oxide Failure Evaluated by Raman Spectroscopy

On the Origin of the Gate Oxide Failure Evaluated by Raman Spectroscopy

Design on Formation of Nickel Silicide by a Low‐Temperature Pulsed Laser Annealing Method to Reduce Contact Resistance for CMOS Inverter and 6T‐SRAM on a Wafer‐Scale Flexible Substrate

Effect of Vacuum Annealing Temperature on the Binary System Ni/Si(100)

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