NIOS II processor-based acceleration of motion compensation techniques

Real-Time Motion Processing Estimation Methods in Embedded Systems

“…This representation calculates an image where each pixel's value is a mean of itself with its neighbourhood; after that, the image is under sampled to the half, as shown in Figure 13c. This model is implemented using the Altera DE2 board and the Cyclone II FPGA as shown in the Figures 11b and 12b (González et al, 2011), balancing the code between the microprocessor implemented and the acceleration system which uses Avalon Bus thanks to so-called "C to hardware compiler" from Altera (Altera, 2011). …”

“…The parameters for measuring the resources for this technology are Logic Cell and Embedded DSPs. For this implementation, we have used different embedded NIOS II microprocessors (E, S, F from "economic", "standard", and "full" with different characteristics (González et al, 2011) and for each one of these microprocessors we have applied different parts of the code, distinguishing between "Quality I, II or III" depending of the piece of the code running just into the microprocessor and the part that is accelerated using C2H compiler. (Altera, 2011).…”

“…• Botella et al implemented a robust gradient based optical flow real-time system and its extension to mid-level vision combining orthogonal variant moments (Botella et al, 2009(Botella et al, , 2010. Also the block matching acceleration motion estimation has been implemented in real-time by Gonzalez and Botella (González et al, 2011). All these models will be analyzed thoroughly in this chapter.…”