Nitridation of Si by N[sub 2] Electron Cyclotron Resonance Plasma and Integration with ScO[sub x] Deposition

Abstract

Nitridation of silicon was achieved by exposure of silicon to N 2 electron cyclotron resonance plasma. The growth rate decreased as the nitridation time increased due to the growth process being limited by the diffusion of nitrogen through the growing SiN x layer. The thickness of the SiN x layer was about 1.5 nm for a nitridation time of 30 s, according to ellipsometry and transmission electron microscopy measurements. Additionally, scandium oxide ͑ScO x ͒ films were deposited by high pressure sputtering on top of the nitrided silicon, as well as in reference un-nitrided silicon, to study the influence of the nitridation process on the interface properties. The silicon nitride layer is efficient in preventing the growth of interfacial silicon oxide. The minimum of the density of interface traps ͑D it,min ͒ for ScO x /SiN x /Si structures with 30 s nitridation was around 2 ϫ 10 11 cm −2 eV −1 , indicating an improvement with respect to the ScO x deposition on un-nitrided silicon with D it,min of about 1.2 ϫ 10 11 cm −2 eV −1 . The best interface quality was obtained for the shortest nitridation time of 30 s. Finally, it was observed that the nitridation process greatly inhibits interface reaction during rapid thermal annealing at 1000°C.The continuous scaling of the metal-oxide-semiconductor ͑MOS͒ transistor has led to reaching the limits of silicon oxide as a gate dielectric due to the impossibility of further reducing its thickness. Therefore, to meet the requirements of the 45 nm technology generation and beyond, silicon oxide must be replaced by a high dielectric constant ͑high-k͒ material, which allows physically thicker insulator films with the same capacitance as a thinner silicon oxide film. 1 The fabrication of 45 nm technology microprocessors using transistors with a gate structure based on hafnium oxide, together with an appropriate gate metal, has already been reported by Intel. 2 Logic technologies for the 32 nm generation have also been reported. 3-5 However, research to further improve the properties or to find new high-k dielectrics is still required.One subject of great concern is the control of the interface between the high-k dielectric and the substrate to prevent the growth of an undesired silicon oxide interface layer during the deposition of the high-k dielectric or during postdeposition annealing. 6 The presence of such a low-k interface layer places a limit on the equivalent oxide thickness of the gate insulator that can be achieved. Additionally, when this silicon oxide grows in an uncontrolled way, it may lead to high densities of interface traps.The incorporation of nitrogen into the interface, therefore forming a silicon nitride or silicon oxynitride layer, and its influence on the properties of gate structures using high-k dielectrics have been reported by many authors. The nitridation of silicon can be achieved by thermal processing in NO or NH 3 atmospheres 7-12 or by different plasma techniques, such as NH 3 /N 2 and N 2 O/N 2 plasmas, 13 N 2 remote plasma, 12,14 a Xe/NH 3 microwa...

Nano-laminate vs. direct deposition of high permittivity gadolinium scandate on silicon by high pressure sputtering

“…The shift towards lower wavenumber with respect to the ideal SiO 2 band is related 6 to the fact that the interface consists of Si suboxide and/or a stressed interfacial layer [23]. The bands that appear at ~820 and ~910 cm -1 are attributed to the correction of spectra with Si substrate and have been observed in previous works [18,27,28].…”