No Clean Flux technology for large die flip chip packages

Horibe, Akihiro; Lee, Kangwook; Okamoto, Keishi; Mori, Hiroyuki; Orii, Yasumitsu; Nishizako, Yuki; Сузукі, Осаму; Shirai, Y.

doi:10.1109/ectc.2013.6575648

Cited by 6 publications

(3 citation statements)

References 7 publications

(6 reference statements)

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“…This flux is free of volatile organic compounds and is activated and evaporated at the melting-temperature of the Sn-Ag-Cu solder-alloy [17]. As it does not require any postbonding solvent-rinse, there is a very low risk of displacing contaminants onto the optical interfaces of the PIC, making it ideal for photonic-packaging [18], [19]. To illustrate the advantages of this new approach, we compare thermo-compression bonding, solder-reflow bonding without flux, and solder-reflow bonding with the "no-clean" flux on the test-chips.…”

Section: Electronic-photonic Integrationmentioning

confidence: 99%

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Lee¹,

Carroll²,

Scarcella³

et al. 2016

IEEE J. Select. Topics Quantum Electron.

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Integrated photonics is a promising route toward high-performance next-generation ICT and sensing devices. Although fiber-packaging is perhaps the most widely discussed obstacle to low-cost photonic devices, electronic-photonic integration and thermal-stabilization are also significant design considerations that need to be properly managed. Using a state-of-the-art Si-photonic optical-network-unit as a worked example, we illustrate some key challenges and solutions in the field of photonicpackaging. Specifically, we describe a novel solder-reflow bonding process for the face-to-face three-dimensional (3-D) integration of photonic and electronic integrated circuits, discuss current and future multichannel fiber-alignment techniques, and investigate the coefficient-of-performance of the thermo-electric cooler that stabilizes the temperature of the photonic components. The challenge of photonic-packaging is to simultaneously satisfy these electrical, optical, and thermal design requirements on small-footprint devices, while establishing a route to scalable commercial implementation.

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Section: Electronic-photonic Integrationmentioning

confidence: 99%

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Lee¹,

Carroll²,

Scarcella³

et al. 2016

IEEE J. Select. Topics Quantum Electron.

View full text Add to dashboard Cite

show abstract

“…Instead, a 'no clean' flux should be used during the solder-reflow bonding. This flux is VOC-free (volatile organic compounds) and activates and evaporates at the melting-point of the solder [52], so it does not require a post-bonding solvent-rinse that can contaminate the PIC [53,54].…”

Section: Vertical Integrationmentioning

confidence: 99%

Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices

et al. 2016

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Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

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“…Instead, the ONU was assembled with a new "no clean" flux solder-reflow process, using a VOC-free (Volatile Organic Compounds) flux that activates and then evaporates at the melting-temperature of the solder-cap [8]. This means that no post-bonding solvent-rinse is needed, minimizing the risk of displacing contaminants onto the grating-couplers on the surface of the PIC [9,10]. As shown in Fig.…”

Section: Assembly Of Packaged Modulementioning

confidence: 99%

Demonstration of a Partially Integrated Silicon Photonics ONU in a Self-Coherent Reflective FDMA PON

Straullu

Savio

Franco

et al. 2017

J. Lightwave Technol.

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We report about the final results of the FABULOUS European project, demonstrating the feasibility of real-time Ethernet transmission on a self-coherent reflective Passive Optical Network, using an Optical Network Unit whose main optical functions are performed by a silicon-photonics device; 500 Mbps per user with a power budget of 24 dB in offline processing and 21 dB in real-time is shown. We also report details about the packaging process and the special technique developed for the flip-chipping of a CMOS electrical driver, used for driving the ONU with low voltage, onto a Silicon Mach

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No Clean Flux technology for large die flip chip packages

Abstract: A new No Clean Flux (NCFx) material for large die packages was formulated, which has good wettability for area array lead-free solder bumps of 20  20 mm dies, and which doesn't leave any liquid residues under the die.

Cited by 6 publications

References 7 publications

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices

Demonstration of a Partially Integrated Silicon Photonics ONU in a Self-Coherent Reflective FDMA PON

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