NoC Power Estimation at the RTL Abstraction Level

Guindani, Guilherme; Reinbrecht, Cezar; Raupp, Thiago; Calazans, Ney; Moraes, Fernando

doi:10.1109/isvlsi.2008.17

Cited by 33 publications

(12 citation statements)

References 8 publications

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“…Clearly most of the power is consumed by the input modules, as shown by previous work [8,13], but the effect is weaker in soft NoCs than in hard. This also conforms with the area composition of the routers; most of the router area is dedicated to buffering in the input modules, while the smallest router component is the crossbar [1].…”

Section: Router Power Compositionmentioning

confidence: 59%

“…However, there is an extensive body of work discussing the power consumption of NoCs for multiprocessors. Some papers discuss the power breakdown of NoCs by router components and links, and investigate how power varies with different data injection rates in an NoC [8][9][10]. Other work focuses on complete systems and reports the power budgeted for communication using an NoC [11,12].…”

Section: Introductionmentioning

confidence: 99%

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The power of communication: Energy-efficient NOCS for FPGAS

Abdelfattah

Betz

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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Integrating networks-on-chip (NoCs) on FPGAs can improve device scalability and facilitate design by abstracting communication and simplifying timing closure, not only between modules in the FPGA fabric but also with large "hard" blocks such as high-speed I/O interfaces. We propose mixed and hard NoCs that add less than 1% area to large FPGAs and run 5-6× faster than the soft NoC equivalent. A detailed power analysis, per NoC component, shows that routers consume 14× less power when implemented hard compared to soft, and whether hard or soft most of the router's power is consumed in the input modules for buffering. For complete systems, hard NoCs consume less than 6% (and as low as 3%) of the FPGA's dynamic power budget to support 100 GB/s of communication bandwidth. We find that, depending on design choices, hard NoCs consume 4.5-10.4 mJ of energy per GB of data transferred. Surprisingly, this is comparable to the energy efficiency of the simplest traditional interconnect on an FPGA -soft point-to-point links require 4.7 mJ/GB. In many designs, communication must include multiplexing, arbitration and/or pipelining. For all these cases, our results indicate that a hard NoC will be more energy efficient than the conventional FPGA fabric.

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Section: Router Power Compositionmentioning

confidence: 59%

Section: Introductionmentioning

confidence: 99%

The power of communication: Energy-efficient NOCS for FPGAS

Abdelfattah

Betz

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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“…Actually, it is an unfeasible task to accurately predict latency of a complicated system by static models. Likewise, the power consumption analysis, such as using some high level power analysis tools [131,180,133] or modeling power analysis [23,171,64,84,49,90], suffers from more inaccuracies without gate-level parameters and switching activities. The high abstraction models are very hard to determine with accuracy in the early development stages.…”

Section: Verification and Performance Evaluation Methodologymentioning

confidence: 99%

“…An earlier stage performance evaluations, such as transfer latency [181] and wire efficiency models [108,88], and several high-level power analysis tools [133,64,90,171,84], allow engineers to design circuits more efficiently, reducing the time costs and risk of error involved in building circuit prototypes. For these mathematical analysis models, large system complexity is a challenge, making the enumeration of the complete design logic difficult, sometimes an unfeasible task.…”

Section: Automatic Performance Evaluationmentioning

confidence: 99%

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

Yang¹

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“…Enabling a single FE to control multiple PEs requires that control logic drive long wires, consuming significant energy. This is especially critical as process technology advancements reduce transistor energy faster than the wire energy, making the energy consumed in wires significant [36]. By changing the partitioning point, a designer can change the number of control signals as well as the shared components and therefore the energy overhead/savings of SIMD operation.…”

Section: System Designmentioning

confidence: 99%

Maximizing Energy Efficiency through Vertically Integrated Dynamic Reconfigurability

Arrabi¹

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Power and energy consumption have become some of the main hurdles for performance advancement in modern digital systems. High transistor densities and clock speeds have created significant thermal and power delivery issues, and increasingly pervasive portable electronic devices have limited energy sources but high performance expectations. Power affects and is affected by almost every aspect of digital system design, enticing designers and researchers to approach this problem from every possible aspect.This work explores two such aspects: dynamic reconfigurability and vertical integration. Dynamic reconfigurability is the ability to change the configuration of the system dynamically during runtime, and vertical integration is using low-level design information in high-level decisions (and vice-versa) as well as co-optimizing multiple design levels simultaneously. Both of these concepts can be targeted to various system metrics; in this work, they are used to reduce the total energy consumption of the system with the goal of increasing system battery lifetime while still providing the necessary performance and functional capabilities.This work explores dynamic reconfigurability and vertical integration through the use of three practical systems. We go through the steps and analysis in designing these systems that will show the potential benefits of our methods. Through the steps of designing the systems, we show the impact of several significant aspects of vertically integrated dynamically configurable systems, thus providing a framework for identifying potential benefits of reconfigurability and co-optimization and for general guidelines of how to implement them on other systems. We also look at the granularity of configurability and the overhead that it incurs, as well as the circuit-level details and information that might affect and be affected by architectural or system-level decisions.The first system is a wireless body sensor node that consumes most of its energy wirelessly transmitting data. We investigate how adaptive software can compress the data before sending without sacrificing information using only the limited processing and memory resources that typically reside on body sensors. We go through the various aspects that affect our solution and the different design levels we have to take into account when applying the compression.The second example system is a custom digital signal-processing system utilizing Panoptic Dynamic Voltage Scaling (PDVS), in which we investigate adding fine-grained spatial and temporal granularities of voltage scaling to the processor. We use a vertically integrated approach to explore the trade-offs of the ability to switch the voltage of a single arithmetic component (spatial) for a single operation (temporal), as well as the different variables that need to be considered for scheduling such systems.The third system is a Field Programmable Core Array (FPCA), in which we investigate various methods for creating a configurable processor capable of switching betwee...

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NoC Power Estimation at the RTL Abstraction Level

Cited by 33 publications

References 8 publications

The power of communication: Energy-efficient NOCS for FPGAS

The power of communication: Energy-efficient NOCS for FPGAS

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

Maximizing Energy Efficiency through Vertically Integrated Dynamic Reconfigurability

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