NOC’S: Buffered and Bufferless Structure and their design methodologies for High throughput and Low latency

Abstract

To know and meet the existing issues and demands related to scalability of number of nodes, their sizes of Network on Chip (NoC) which are important networks for efficient communication to transfer multimedia data at low latency and high throughput. These NoC's was designed and developed the chips for both 2D and 3D which includes switching, routing and crossbar techniques, out of which routing algorithms are plays major role due to the computational operations take place here and produce the different delay. In turn these delays are affected on throughput and latency. Many of the NoC's has buffered and bufferless routers to optimize the area, power consumption and latency. Therefore the detailed literature survey has been done mainly on latest buffered and bufferless NoC's with different routing algorithms used for addressing the major constraints like QoS, throughput, latency and hardware utilizations for different injection rates. As per requirements at present situation for better communication within core networks, this paper mainly focused on commonly used architectures and their inter components connectivity's that can deal with methodologies and design challenges for optimization of signal integrity, scalability, throughput and latency in an NoC's. At the last, modified buffered and bufferless NoC architectures are proposed which includes the modified routing algorithm called Dynamically buffered and bufferless reconfigurable NoC (DB 2 R-NoC's) and feasible direction finding (FDF) for switching. Making use of these architectures, any dimensions of NoC's can be designed and can validate for multimedia data and also can test on Field Programmable Gate Array (FPAG) processors.