Noise analysis and measurement of integrator-based sensor interface circuits for fluorescence detection in lab-on-a-chip applications

Jensen, Karl Andreas; Gaudet, Vincent; Levine, Peter M.

doi:10.1109/icnf.2013.6578905

Cited by 4 publications

(1 citation statement)

References 31 publications

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“…Figure 5D presents estimates of acceptable noise levels for various on/off ratios on the devices β and integration times t meas . This noise level corresponds to the input referred noise of the op-amp calculated using standard noise analysis in integrator-based circuits (Jensen et al, 2013 ). If t meas is taken as 20 ns following the quantization error consideration discussed above, the acceptable noise levels are relatively low of the order of just

5

as seen in Figure 5D curve 1.…”

Section: Resultsmentioning

confidence: 99%

Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices: Design Considerations

Gokmen¹,

Vlasov²

2016

Front. Neurosci.

390

428

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In recent years, deep neural networks (DNN) have demonstrated significant business impact in large scale analysis and classification tasks such as speech recognition, visual object detection, pattern extraction, etc. Training of large DNNs, however, is universally considered as time consuming and computationally intensive task that demands datacenter-scale computational resources recruited for many days. Here we propose a concept of resistive processing unit (RPU) devices that can potentially accelerate DNN training by orders of magnitude while using much less power. The proposed RPU device can store and update the weight values locally thus minimizing data movement during training and allowing to fully exploit the locality and the parallelism of the training algorithm. We evaluate the effect of various RPU device features/non-idealities and system parameters on performance in order to derive the device and system level specifications for implementation of an accelerator chip for DNN training in a realistic CMOS-compatible technology. For large DNNs with about 1 billion weights this massively parallel RPU architecture can achieve acceleration factors of 30, 000 × compared to state-of-the-art microprocessors while providing power efficiency of 84, 000 GigaOps∕s∕W. Problems that currently require days of training on a datacenter-size cluster with thousands of machines can be addressed within hours on a single RPU accelerator. A system consisting of a cluster of RPU accelerators will be able to tackle Big Data problems with trillions of parameters that is impossible to address today like, for example, natural speech recognition and translation between all world languages, real-time analytics on large streams of business and scientific data, integration, and analysis of multimodal sensory data flows from a massive number of IoT (Internet of Things) sensors.

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5

as seen in Figure 5D curve 1.…”

Section: Resultsmentioning

confidence: 99%

Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices: Design Considerations

Gokmen¹,

Vlasov²

2016

Front. Neurosci.

390

428

View full text Add to dashboard Cite

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Microfluidic devices: a road forward by standardization of interconnects and classification

Heeren¹,

Tantra

Salomon

2015

Microfluid Nanofluid

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A potentiostat featuring an integrator transimpedance amplifier for the measurement of very low currents—Proof-of-principle application in microfluidic separations and voltammetry

Koutilellis

Economou

Efstathiou

2016

Review of Scientific Instruments

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This work reports the design and construction of a novel potentiostat which features an integrator transimpedance amplifier as a current-monitoring unit. The integration approach addresses the limitations of the feedback resistor approach used for current monitoring in conventional potentiostat designs. In the present design, measurement of the current is performed by a precision switched integrator transimpedance amplifier operated in the dual sampling mode which enables sub-pA resolution. The potentiostat is suitable for measuring very low currents (typical dynamic range: 5 pA-4.7 μA) with a 16 bit resolution, and it can support 2-, 3- and 4-electrode cell configurations. Its operation was assessed by using it as a detection module in a home-made capillary electrophoresis system for the separation and amperometric detection of paracetamol and p-aminophenol at a 3-electrode microfluidic chip. The potential and limitations of the proposed potentiostat to implement fast potential-scan voltammetric techniques were demonstrated for the case of cyclic voltammetry.

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Noise analysis and measurement of integrator-based sensor interface circuits for fluorescence detection in lab-on-a-chip applications

Cited by 4 publications

References 31 publications

Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices: Design Considerations

Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices: Design Considerations

Microfluidic devices: a road forward by standardization of interconnects and classification

A potentiostat featuring an integrator transimpedance amplifier for the measurement of very low currents—Proof-of-principle application in microfluidic separations and voltammetry

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