Noise and PVT Tolerant, High-Speed and Energy-Efficient Hybrid 4-2 Compressor in CNFET Technology

Abstract

In this paper, a novel high-speed and energy efficient 4 − 2 compressor cell is proposed using Carbon Nanotube Field Effect Transistors (CNFETs). The proposed compressor is realized efficiently based on NAND-NOR gates and multiplexers. To estimate the performance of the presented design, simulations are carried out using Synopsis HSPICE under different conditions. The results demonstrate the performance improvement of the proposed design compared to the best reference designs in terms of delay and energy consumption, by 20 and 26%, respectively. Also, the susceptibility of the proposed design against the process, voltage, temperature (PVT), and noise variations is examined. It is robust against PVT variations and high amplitude of noises compared with its counterpart. Also, it displays the most robustness, in terms of PVT variations compared with its counterpart. Furthermore, it has the best results in large structures, such as a multiplayer. Furthermore, embedding the proposed compressor in an 8× 8-bit binary multiplier demonstrates that it has better speed and PDP with regard to its counterparts.