Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Abstract

Dual-rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual-rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan-in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual-rail circuits such as differential domino logic and differential cross-coupled domino logic. Simulation results for 32-bit-wide OR gates designed using high-performance 16-nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise-immunity improvement at the same delay compared to the differential domino circuits.

A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

“…For this reason, the time delay has squared. As mentioned in [47], use of the powers other than those used here for the five factors of interest is also possible. The defined figure of merit (FOM) is limited by some parameters such as frequency, temperature, technology node and supply voltage.…”

“…In the absence of a well defined and comprehensive figure of merit to account for noise, delay, power, and area together, a figure of a merit (FOM) have been previously proposed for the design of a logic gate such as OR gates [47]. It was defined as follows:…”

Low Leakage Low Power Domino Logic Technique for Wide Fan-In Applications, 40-Bit Tag Comparator

“…A measure used to compare the effectiveness of existing techniques with proposed technique in terms of delay, power, area and noise is known as Figure of Merit (FOM) [7,[23][24]. It is expressed as; The simulation results of proposed 8-input OR gate with literature techniques are summed up in Table 3, under same UNG criteria.…”