Noise Reduction Using Modified Wiener Filter in Digital Hearing Aid for Speech Signal Enhancement

Abstract

<jats:title>Abstract</jats:title><jats:p>Speech signals are usually affected by noises during the communication process. For suppressing the noise signal that is combined with the speech signal, a Wiener filter is adapted in digital hearing aids. Weiner filter plays an important role in noise suppression and enhancement by estimating the relation between the power spectra of the noise-affected speech signal and the noise signal. Power consumption and the hardware requirement are the important problems in adapting Weiner filter for major communication systems. In this work, we implemented an efficient Wiener filter and applied it for noise suppression along with a real-valued fast Fourier transform (FFT)/real-valued inverse FFT processor in digital hearing aids. The pipelined process was adopted for increasing the performance of the system. The proposed Wiener filter was designed to remove the iteration problems in the conventional Wiener filter. The division operation was replaced by an efficient inverse and multiplication operation in the proposed design. A modified architecture for matrix inversion with low computation complexity was implemented. The complete design computation was based on IEEE-754 standard single-precision floating-point numbers. The Wiener filter and the whole system architecture was implemented and designed on a Field Programmable Gate Array platform and simulated to validate the results in Xilinx ISE tools. An efficient reduction in power and area was obtained by adapting the proposed method for speech signal noise degradation. The performance of the proposed design was found to be 50.01% more efficient than that of existing designs.</jats:p>

High-Radix Formats for Enhancing Floating-Point FPGA Implementations

“…Taking into account that the number of bits of the exponent is given by 8 − log 2 r (see expression (15)), the smallest value for the exponent is E x min = −2 8−log 2 r −1 . On the other hand, the largest value of the exponent is E x max = 2 8−log 2 r −1 − 1.…”

“…5. All parameters of Table 1 are derived from expressions (3), ( 4), (15) and (17). The first row shows the parameters for the radix 2 IEEE 754 single precision.…”

“…In those heterogeneous architectures, generally, the FPGA is used as an accelerator to implement the most demanding task of the system. Although fixedpoint arithmetic has been used traditionally in FPGA, in this model, the utilization of floating-point arithmetic is preferred for many applications such as advanced signal processing [6,7,15], industrial [16,17,20], wireless communication [8,21], and other advanced applications [11][12][13][14]18,19,22]. Although the fixed-point number operation has the advantages of fast computation and easy implementation, floating-point (FP) arithmetic offers a larger dynamic range and higher numeric stability.…”