Noise-tolerant high fan-in dynamic CMOS circuit design

Abstract

Scaling CMOS technology to next generation improves performance, increases transistor density, and reduces power consumption per device. However, scaling also increases the subthreshold leakage current which greatly degrades the circuit's noise immunity. In this paper we propose a new circuit technique that makes domino dynamic CMOS more robust and more noisetolerant with minimal performance degradation and energy overhead. Simulations for high fan-in gates show a noise immunity improvement of 2.13X using Berkeley Predictive Technology Models (BPTM) of 70nm with minimal performance and power degradations over standard domino circuits.

An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance

“…Many design techniques [10], [11], [12], [13] have been developed previously for improving the noise tolerance of dynamic circuits. For increasing the switching threshold a skewed CMOS is designed for each input adding a extra transistor.…”

Robustness aware high performance high fan-in domino OR logic design

“…Considering the stack effect of NMOS transistors, an alternative domino design technique was proposed in Ref. [3] to achieve a great improvement in performance and noise immunity, but this technique leads to a considerable penalty of power consumption. The diode-footed domino technique in Ref.…”