Non-Backtracking Reconfiguration Algorithm for Three-dimensional VLSI Arrays

Abstract

Fast reconfiguration is one of the main challenges in fault tolerant VLSI arrays. In these arrays, there are some invalid processing elements (PEs) that are fault-free but cannot be used to form a target array. These invalid PEs lead to backtracking in reconfiguration. This paper proposes a non-backtracking reconfiguration (NBR) algorithm for three-dimensional degradable VLSI array with faults. The proposed algorithm accelerates the reconfiguration without loss of harvest, by eliminating the backtracking operation that frequently occurs in the existing algorithm (named as BGPR) cited in this paper. Initially, the invalid PEs are identified in the preprocessing for the host array. Then NBR algorithm constructs each logical plane from bottom to top in the host array, and updates the set of the invalid PEs in the host array after a logical plane is constructed. Experimental results show that the NBR algorithm is more scalable than the BGPR algorithm, and thus it can reconfigure large host arrays much faster. In addition, the runtime of NBR algorithm tends to decrease, rather than increase as did in BGPR algorithm, with the increasing fault density.Index Terms-3D VLSI array, reconfiguration, fault tolerant, non-backtracking algorithm.

Efficiency of Flexible Rerouting Scheme for Maximizing Logical Arrays

“…In this section, we investigate the efficiency of flexible rerouting scheme by evaluating performance of algorithm FLX in comparison with algorithm GCR. To evaluation metrics, i.e., harvest and degradation, as formulated in [8][9][10][13][14], were calculated. The harvest indicates how effectively the non-faulty elements are utilized in constructing a target array from a host array with fault elements, whereas the degradation measures the degree of potential performance loss due to a smaller target array than the original host array.…”

“…For the simplicity, we denote target arrays constructed by algorithms GCR and FLX as GCRA and FLXA, respectively. The improvement in harvest of the FLX over algorithm GCR, is calculated by In order to make a fair comparison, we keep the same assumptions as in [8][9][10][11][12][13][14]. Faults are only associated with PEs and communication infrastructure is assumed to be fault free.…”

“…In [12], novel techniques are presented to accelerate reconfiguration by employ flexible upper and lower bounds for the maximum logical array (MLA). The degradable reconfiguration approach for three-dimensional mesh-connected processor arrays is investigated in [13] [14].…”