Non-blocking programmable delay line with minimal dead time and tens of picoseconds jitter

Abstract

We report a non-blocking high-resolution digital delay line based on an asynchronous circuit design. Field-programmable gate array logic primitives were used as a source of delay and optimally arranged using combinatorial optimization. This approach allows for an efficient trade-off of the resolution and a delay range together with a minimized dead time operation. We demonstrate the method by implementing the delay line adjustable from 23 ns up to 1635 ns with a resolution of 10 ps. We present a detailed experimental characterization of the device focusing on thermal instability, timing jitter, and pulse spreading, which represent three main issues of the asynchronous design. We found a linear dependence of the delay on the temperature with the slope of 0.2 ps K−1 per logic primitive. We measured the timing jitter of the delay to be in the range of 7–165 ps, linearly increasing over the dynamic range of the delay. We reduced the effect of pulse spreading by introducing pulse shrinking circuits and reached the overall dead time of 4–22.5 ns within the dynamic range of the delay. The presented non-blocking delay line finds usage in applications where the dead time minimization is crucial, and tens of picoseconds of excess jitter is acceptable, such as in many advanced photonic networks.

Picosecond programmable delay line using commercial components for precision timing signal alignment

“…sub-picosecond) delays are required. Digital delay methods can achieve picosecond level precision using both field-programmable gate arrays (FPGAs) [6][7][8][9][10] and commercially available digital delay devices (e.g. MC100EP195 from OnSemi, DS1023 from Analog Devices, HM856 from Analog Devices, SY89297U from Microchip) [11][12][13].…”